Truncated ternary multipliers

Parhami, Behrooz

doi:10.1049/iet-cdt.2013.0133

Cited by 8 publications

(3 citation statements)

References 34 publications

(31 reference statements)

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“…Radices other than two, eight, ten, and sixteen were mostly ignored earlier [12]. However, radices three and four are used to implement multivalued logic (MVL), which improves the data transmission capability and computational speed [13].…”

Section: • Multi Walled Cntsmentioning

confidence: 99%

Low power CNTFET-based ternary multiplier for digital signal processing applications

Chauhan,

Bansal

2024

Eng. Res. Express

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Multiplication is a fundamental arithmetic process, although it necessitates more hardware resources. Researchers in advanced technology attempted to boost the speed and lower the power in digital signal processing applications by utilizing multipliers. The majority of digital signal processing applications demanded increased speed. In addition, ternary logic based on CNTFETs is a feasible alternative for Si-MOSFETs. The article proposes a ternary multiplier, which is designed using proposed ternary logical and combinational circuits that includes STI, TNAND, TNOR, and ternary decoder. The proposed and existing designs are simulated, compared, and analysed on the parameters of delay, average power, and noise using the HSPICE simulator. Therefore, the results show 10%, 81% and 81% improvement in delay, average power, and PDP respectively for proposed TMUL. The noise margin of the proposed TMUL is increased up to 54% over existing circuits. The proposed TDecoder, STI, TNAND, and TNOR are 95%, 97%, 81%, and 95% more energy efficient than existing designs, respectively.

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Section: • Multi Walled Cntsmentioning

confidence: 99%

Low power CNTFET-based ternary multiplier for digital signal processing applications

Chauhan,

Bansal

2024

Eng. Res. Express

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“…Balanced ternary system [18,19] consists of a base = 3 and a digit set = {1 ̅ , 0, 1} is an example of the system that has this property. In 2005, Kornerup and Muller [7] introduced a generalization of round-to-nearest number system called RNcoding which was defined in definition 4.…”

Section: Round-to-nearest Number Systemmentioning

confidence: 99%

On-line Digit Set Conversion for Rational Digit Number

Thienprapasith¹,

Surarerks²

2017

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Abstract.A number system that is well-designed can affect the computational time and the hardware implementation. An interesting number system called Round-to-Nearest coding (RN-coding) was proposed to reduce a time consuming in a rounding process. Rounding to the nearest in RN-coding can be done using only truncation at any positions in a sequence of digits (representation). This concept can save a lot of time in a parallel or pipeline computation manner. However, an RN-coding does not support an on-line arithmetic computation. In this paper, we propose a rational digit number system which is composed of rational signed-digits in the digit set. This new system preserves a roundto-nearest property and is suitable for an on-line arithmetic computation. Performing online elementary arithmetic operations in our system can be done by an on-line digit set conversion algorithm. We show that our new algorithm, which is an improvement of an on-line addition algorithm in our previous work, can be demonstrated by an on-line finite automaton with a finite on-line delay .

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“…Base 2 is suitable for computational structures due to the effortless and reliable binary devices, thus that base dominates the computer industry [2][3][4][5][6]. Difficulties and limitations of efficient computational structures designs for base 3 prevented researchers to pursue this technology [7]. During the last decade, the advent and the discovery of emerging technologies have brought new opportunities for the maturation of ternary valued logic in the semiconductor industry [8][9][10][11][12][13].…”

Section: Introductionmentioning

confidence: 99%

Novel CNFET ternary circuit techniques for high‐performance and energy‐efficient design

Tabrizchi

Taheri

Navi

et al. 2019

IET Circuits, Devices & Systems

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Here, the authors propose a new family of ternary circuits for a general design perspective. Besides presenting an efficient ternary logical circuit approaches, the focus of this study is also about introducing techniques for reducing the performance metric cost of the proposed family. Basic ternary arithmetic gates, ternary half-adder, and ternary partial product generator are also proposed for two different levels. First, direct transistor level implementation is considered, next a modification in the gate level implementation representing a state-of-the-art approach is addressed. Carbon nanotube FET (CNFET) is considered as an appropriate technology for implementation and realisation of ternary circuits. Therefore, simulations are carried out at 32 nm CNFET model using Synopsis HSpice tool. Simulation results show the advantages of ternary structures considering the proposed method.

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Truncated ternary multipliers

Cited by 8 publications

References 34 publications

Low power CNTFET-based ternary multiplier for digital signal processing applications

Low power CNTFET-based ternary multiplier for digital signal processing applications

On-line Digit Set Conversion for Rational Digit Number

Novel CNFET ternary circuit techniques for high‐performance and energy‐efficient design

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