Trifecta: A Nonspeculative Scheme to Exploit Common, Data-Dependent Subcritical Paths

Ndai, Patrick; Rafique, Nauman; Thottethodi, Mithuna; Ghosh, Swaroop; Bhunia, Swarup; Roy, Kaushik

doi:10.1109/tvlsi.2008.2007491

Cited by 25 publications

(12 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Only some specific instruction sequences and operand values can bring about timing errors [18,19,24]. The former determines which set of critical paths will be exercised, while the latter determines the input vectors of these critical paths.…”

Section: Locality Of Timing Errors In Instruction Levelmentioning

confidence: 99%

See 1 more Smart Citation

Light-weight one-cycle timing error correction based on hardware software co-design

Ding

Yan

et al. 2016

IEICE Electron. Express

View full text Add to dashboard Cite

A light-weight one-cycle EDAC (timing error detection and correction) technique is proposed to eliminate timing margins resulting from process, voltage, temperature and aging (PVTA) variations. The collaborative approach applies TEDPI (timing error deletion programming interface) to pre-detect most of the errors through an offline error prediction model, and pre-correct them at compilation time by using a specially designed error avoidance instruction. Experimental results based on a three-stage commercial processor show that TEDPI has improved peak performance of the traditional EDAC system by 15.6% and reduced the energy consumption by 4.4% with less than 0.71% area overhead.

show abstract

Section: Locality Of Timing Errors In Instruction Levelmentioning

confidence: 99%

“…Most of the timing errors are distributed in execution units [17,18,19,22,24]. For example, the authors in [17] present that errors in the LEON3 processor are distributed between ALU (arithmetic and logic unit, 24%), address generation (25%), result bus (29%) and control logic (22%).…”

Section: Locality Of Timing Errors In Instruction Levelmentioning

confidence: 99%

Light-weight one-cycle timing error correction based on hardware software co-design

Ding

Yan

et al. 2016

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…systems that allow timing errors) where researchers face the long simulation times of variability effects at the architecture level [12][13][14][15][16]. The lack of fast simulation platforms for these systems is becoming a bottleneck and a key challenge for erroneous systems research [4], [14].…”

Section: Related Workmentioning

confidence: 99%

“…The following are some examples of variability management techniques in which the analysis of dynamic error behavior has been limited. Trifecta [12] focuses only on the ALU adder and selection logic. Roy and Chakarborty [13] only consider ALU errors and limit their simulations to 100 instructions that most frequently exercise the ALU.…”

Section: Related Workmentioning

confidence: 99%

Timing analysis of erroneous systems

Assare

Gupta

2014

Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis

View full text Add to dashboard Cite

Erroneous systems allow timing errors to occur during execution, but use measures to ensure continued operation through changes in operating parameters (voltage and frequency), error correction at various levels of the system, or ensuring controlled occurrence of errors to perform approximate computing. In this paper, we are interested in characterization of error behavior at the level of instructions and programs. We propose Inter-and Intra-Program Variation as measures of error rate variability in different programs and among instructions of a program, respectively. We also characterize the error rate variation caused by the program input data and show that it is comparable to other sources of variability such as process variation. Finally, we present an analysis of the physical location of errors in hardware, identify regions in which most of the errors occur, and how different programs change the distribution of errors among these regions. In order to enable reliable timing analysis of large programs, we propose Clustered Timing Model (CTM), a high level timing model based on clustering functionally similar timing paths of the processor, and develop a CTM for LEON3, a representative in-order RISC processor. The accuracy of the model is verified using our variation-aware timing analysis framework with an average error of 3.9% (max. 6.7%) across a wide range of voltage-temperature corners.

show abstract

“…In the proposed approach, the highly affected IFUs are turned off whenever the processor does not require them for running an application and turned on when required. An architectural technique (Trifecta) to mitigate the timing variations in critical pipeline stages is proposed in [6]. In the proposed technique, the inputs that make the critical path delay exceed the onecycle delay are detected (circuit level speculation) and let the path to complete its operation in two-cycles.…”

Section: Related Workmentioning

confidence: 99%

An architecture-level approach for mitigating the impact of process variations on extensible processors

Kamal

Afzali-Kusha

Safari

et al. 2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

View full text Add to dashboard Cite

Abstract-In this paper, we present an architecture-level approach to mitigate the impact of process variations on extended instruction set architectures (ISAs). The proposed architecture adds one extra cycle to execute custom instructions (CIs) that violate the maximum allowed propagation delay due to the process variations. Using this method, the parametric yield of manufactured chips will greatly improve. The cost is an increase in the cycle latency of some of the CIs, and hence, a slight performance degradation for the extensible processor architectures. To minimize the performance penalty of the proposed approach, we introduce a new merit function for selecting the CIs during the selection phase of the ISA extension design flow. To evaluate the efficacy of the new selection method, we compare the extended ISAs obtained by this method with those selected based on the worst-case delay. Simulation results reveal that a speedup improvement of about 18% may be obtained by the proposed selection method. Also, by using the proposed merit function, the proposed architecture can improve the speedup about 20.7%.

show abstract

Trifecta: A Nonspeculative Scheme to Exploit Common, Data-Dependent Subcritical Paths

Cited by 25 publications

References 18 publications

Light-weight one-cycle timing error correction based on hardware software co-design

Light-weight one-cycle timing error correction based on hardware software co-design

Timing analysis of erroneous systems

An architecture-level approach for mitigating the impact of process variations on extensible processors

Contact Info

Product

Resources

About