Trident: From High-Level Language to Hardware Circuitry

Tripp, Justin L.; Gokhale, Maya; Peterson, K.D.

doi:10.1109/mc.2007.107

Cited by 57 publications

(25 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…Delft No Trident [38] Los Alamos NL No CHiMPS [35] U. Washington No Kiwi [18] U. Cambridge Yes gcc2verilog [21] U. Korea No HercuLeS [27] Ajax Compiler No a Refers to array partitioning as part of the tool flow, the arrays can always be re-written into multiple partitions by the software designer.…”

Section: Memory Partitioning In Hlsmentioning

confidence: 99%

Automated generation of banked memory architectures in the high-level synthesis of multi-threaded software

Chen

Anderson

2017

2017 27th International Conference on Field Programmable Logic and Applications (FPL)

View full text Add to dashboard Cite

The Legup High-Level Synthesis (HLS) tool permits the synthesis of multi-threaded software into parallel hardware, where parallel software threads are realized as concurrently operating hardware units. A common performance bottleneck in any parallel implementation is memory bandwidth -parallel threads demand concurrent access to memory resulting in contention that hurts performance. FPGAs contain an abundance of independently accessible memories offering high internal memory bandwidth.We describe an approach for leveraging such bandwidth in the context of synthesizing parallel software into hardware. Our approach applies trace-based profiling to determine how a program's arrays should be automatically partitioned into sub-arrays, which are then implemented in separate RAM blocks within the target FPGA. The end result is that each thread, when implemented in hardware, has exclusive access to its own memories to the extent possible, significantly reducing contention and arbitration and thus raising performance.ii

show abstract

Section: Memory Partitioning In Hlsmentioning

confidence: 99%

Automated generation of banked memory architectures in the high-level synthesis of multi-threaded software

Chen

Anderson

2017

2017 27th International Conference on Field Programmable Logic and Applications (FPL)

View full text Add to dashboard Cite

show abstract

“…FPGAs have continually improved in capacity and speed in recent years, and their programmability makes them an attractive platform for many applications in signal processing, communication, and HPC. There has been a strong desire to make FPGA programming easier, and many HLS tools are designed to specifically target FPGAs, including ASC [65], CASH [9], C2H [99], DIME-C [114], GAUT [23], Handel-C Compiler (now part of Mentor Graphics DK Design Suite) [96], Impulse C [75], ROCCC [88], [40], SPARK [41], [42], Streams-C [37], and Trident [83], [84]. ASIC tools also commonly provide support for targeting an FPGA tool flow in order to enable system emulation.…”

Section: B Recent Effortsmentioning

confidence: 99%

High-Level Synthesis for FPGAs: From Prototyping to Deployment

Cong

Liu

Neuendorffer

et al. 2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

651

272

View full text Add to dashboard Cite

Abstract-Escalating system-on-chip design complexity is pushing the design community to raise the level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of early generations of commercial high-level synthesis (HLS) systems, we believe that the tipping point for transitioning to HLS methodology is happening now, especially for field-programmable gate array (FPGA) designs. The latest generation of HLS tools has made significant progress in providing wide language coverage and robust compilation technology, platform-based modeling, advancement in core HLS algorithms, and a domain-specific approach. In this paper, we use AutoESL's AutoPilot HLS tool coupled with domain-specific system-level implementation platforms developed by Xilinx as an example to demonstrate the effectiveness of state-of-art C-to-FPGA synthesis solutions targeting multiple application domains. Complex industrial designs targeting Xilinx FPGAs are also presented as case studies, including comparison of HLS solutions versus optimized manual designs. In particular, the experiment on a sphere decoder shows that the HLS solution can achieve an 11-31% reduction in FPGA resource usage with improved design productivity compared to hand-coded design.Index Terms-Domain-specific design, field-programmable gate array (FPGA), high-level synthesis (HLS), quality of results (QoR).

show abstract

“…Optimizing compiler research infrastructures are key elements in many research communities including High Performance Computing [4] and Embedded Systems Design Automation [5]. Optimizing compilers aim at obtaining the best possible performance from input programs.…”

Section: Optimizing Compiler Researchmentioning

confidence: 99%

Model-Driven Engineering and Optimizing Compilers: A Bridge Too Far?

Floch

Yuki

Guy

et al. 2011

Model Driven Engineering Languages and Systems

View full text Add to dashboard Cite

Abstract. A primary goal of Model Driven Engineering (MDE) is to reduce the cost and effort of developing complex software systems using techniques for transforming abstract views of software to concrete implementations. The rich set of tools that have been developed, especially the growing maturity of model transformation technologies, opens the possibility of applying MDE technologies to transformation-based problems in other domains. In this paper, we present our experience with using MDE technologies to build and evolve compiler infrastructures in the optimizing compiler domain. We illustrate, through our two ongoing research compiler projects for C and a functional language, the challenging aspects of optimizing compiler research and show how mature MDE technologies can be used to address them. We also identify some of the pitfalls that arise from unrealistic expectations of what can be accomplished using MDE and discuss how they can lead to unsuccessful and frustrating application of MDE technologies.

show abstract

Trident: From High-Level Language to Hardware Circuitry

Cited by 57 publications

References 7 publications

Automated generation of banked memory architectures in the high-level synthesis of multi-threaded software

Automated generation of banked memory architectures in the high-level synthesis of multi-threaded software

High-Level Synthesis for FPGAs: From Prototyping to Deployment

Model-Driven Engineering and Optimizing Compilers: A Bridge Too Far?

Contact Info

Product

Resources

About