Triangle Counting Accelerations: From Algorithm to In-Memory Computing Architecture

Wang, Xueyan; Yang, Jianlei; Zhao, Yinglin; Jia, Xiaohong; Yin, Rong; Chen, Xuhang; Qu, Gang

doi:10.1109/tc.2021.3131049

Cited by 9 publications

(1 citation statement)

References 26 publications

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“…To reduce the cost of data movement, the PIM platform has been proposed for several decades [32][33][34]. Some proposals in the context of static RAM (SRAM) or dynamic RAM (DRAM) have been researched in recent years.…”

Section: Pim Architecturesmentioning

confidence: 99%

NAND-SPIN-Based Processing-in-MRAM Architecture for Convolutional Neural Network Acceleration

Zhao,

Yang,

et al. 2022

Preprint

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The performance and efficiency of running large-scale datasets on traditional computing systems exhibit critical bottlenecks due to the existing power wall and memory wall problems. To resolve those problems, processing-in-memory (PIM) architectures are developed to bring computation logic in or near memory to alleviate the bandwidth limitations during data transmission. NAND-like spintronics memory (NAND-SPIN) is one kind of promising magnetoresistive random-access memory (MRAM) with low write energy and high integration density, and it can be employed to perform efficient in-memory computation operations. In this work, we propose a NAND-SPIN-based PIM architecture for efficient convolutional neural network (CNN) acceleration. A straightforward data mapping scheme is exploited to improve the parallelism while reducing data movements. Benefiting from the excellent characteristics of NAND-SPIN and in-memory processing architecture, experimental results show that the proposed approach can achieve ∼2.6× speedup and ∼1.4× improvement in energy efficiency over state-of-the-art PIM solutions.

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Section: Pim Architecturesmentioning

confidence: 99%