Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout

3D Multi-gate Transistors: Concept, Operation, and Fabrication

“…Secondly, the coupling of low surface optical phonon modes, which results from the polarization of high-k dielectric, reduces the electron mobility [27]. This was partly solved by metal/high-k junction at the gate as the metal prevents the coupling of the phonons to the channel under certain conditions improving the mobility [28,29] like Hafnium dioxide -HfO 2 -high-k/TiN metal gate but still the problem of high threshold voltage, also it requires definite type of n-channel and p-channel materials of certain work function for high performance CMOS logic [30]. Now Intel has engineered n-type and p-type metal electrodes that have the correct work functions on the high-K for high-performance CMOS [27,31].…”

Compact Modeling of Carbon Nanotube Transistor and Interconnects

“…As we approach these fundamental limits in planar CMOS process, it becomes imperative to search for alternative materials, structures, devices as well as design paradigm to replace silicon transistor as the building block of future nanoelectronics. Novel structures like FinFETs (Hisamoto et al, 2000) and Trigate devices (Doyle et al, 2003), strained channel to enhance carrier mobility (Welser et al, 1994) and high-K/metal gate to reduce gate leakage current (Chau et al, 2004) have been proposed. These innovations have limited potential and will extend the scaling by a generation or two.…”

Impact of dynamic voltage scaling and thermal factors on FinFET-based SRAM reliability

“…In this context, semiconductor foundries, such as Intel, TSMC and Global Foundries, have been adopting the multi-gate, nonplanar transistor technology known as Fin Field-Effect Transistor, or FinFET [3], [4]. The FinFET is pointed as a promise alternative to improve the performance and energy tradeoffs, while keeping the compatibility with CMOS process [5].…”