Trends of Power Electronic Packaging and Modeling

Liu, Yong; Irving, S.; Luk, Timwah; Kinzer, D.

doi:10.1109/eptc.2008.4763404

Cited by 59 publications

(32 citation statements)

References 23 publications

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“…As SIP will also have thermal heat dissipation (Liu et al 2008;Brunschwiler et al 2009), solder die attach is an issue. Analogous to bump reliability, the creep strain can be integrated along the damage path to yield a value which can be evaluated via a modified Paris-Erdogan equation,…”

Section: Solder Fatiguementioning

confidence: 99%

Lifetime modelling for microsystems integration: from nano to systems

Wunderle

Michel

2009

Microsyst Technol

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Due to the rapid development of IC technology the traditional packaging concepts are making a transition into more complex system integration techniques in order to enable the constantly increasing demand for more functionality, performance, miniaturisation and lower cost. These new packaging concepts (as e.g. system in package, 3D integration, MEMS-devices) will have to combine smaller structures and layers made of new materials with even higher reliability. As these structures will more and more display nano-features, a coupled experimental and simulative approach has to account for this development to assure design for reliability in the future. A necessary ''nano-reliability'' approach as a scientific discipline has to encompass research on the properties and failure behaviour of materials and material interfaces under explicit consideration of their micro-and nano-structure and the effects hereby induced. It uses micro-and nano-analytical methods in simulation and experiment to consistently describe failure mechanisms over these length scales for more accurate and physically motivated lifetime prediction models. This paper deals with the thermo-mechanical reliability of microelectronic components and systems and methods to analyse and predict it. Various methods are presented to enable lifetime prediction on system, component and material level, the latter promoting the field of nano-reliability for future packaging challenges in advanced electronics system integration.

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Section: Solder Fatiguementioning

confidence: 99%

Lifetime modelling for microsystems integration: from nano to systems

Wunderle

Michel

2009

Microsyst Technol

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“…wearables and laptop suppliers, which is positively moving towards cheaper yet powerful devices. To be able to adapt to this fastchanging trend [1][2][3], densification and thinning of integrated circuit (IC) packaging become the interest of semiconductor manufacturing companies. By producing thinner version of QFN, multiple advantages can be derived from this direction such as 1) reduced lead inductance from the internal interconnection of metal carrier and wirings, 2) good thermal and electrical performance due to thin profile between silicon die and printed circuit board (PCB) where lesser distance in between increases the thermal dissipation.…”

Section: Original Research Articlementioning

confidence: 99%

Incorporating Package Grinding Process for QFN Thin Device Manufacturing

Rodriguez¹,

Gomez²

2020

JERR

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Package thinning, down-scaling, and miniaturization are common interests among semiconductor industries, with each manufacturing site having different approach and technical directions in providing novelties in their products. The paper offers an innovative design of manufacturing flow to reduce the semiconductor package height of a Quad-Flat No-leads (QFN) device through the application of a specialized package grinding process. The process would significantly reduce the carrier thickness for the overall package height configuration of QFN. Through this integration, the common assembly barriers and defects related in producing thin devices are eliminated, thus thinner version manufacturing becomes more simplified and efficient.

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“…In producing a QFN device illustrated in Fig. 3, a series of assembly processes from Front-of-line (FOL) and End-of-line stations is required [3][4][5][6][7][8].…”

Section: Design Solution and Improve-mentmentioning

confidence: 99%

Package and Process Design Augmentation of QFN Leadframe Device

Rodriguez¹,

Maming²,

Gomez³

2020

JERR

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Innovations and breakthroughs either through process, equipment or material is known in semiconductor industries as a positive option in overcoming the existing limitations and assembly handicaps. This presentation discusses the assembly methodology and packaging design of a quad-flat no-leads (QFN) devices using grid design molding tool and leadframe with exposed copper tie bar. Realization of this improved package design proposed the removal of mechanical blade as the primary cutting technique of separating the molded leadframes likewise assembly rejection and defect related to the mechanical blade material together with the processing limitations is mitigated as well. Furthermore, the improved design is realized to be a better alternative for manufacturing tighter clearances and unit-unit pitching requirement thus supports densified and critical package design.

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Trends of Power Electronic Packaging and Modeling

Cited by 59 publications

References 23 publications

Lifetime modelling for microsystems integration: from nano to systems

Lifetime modelling for microsystems integration: from nano to systems

Incorporating Package Grinding Process for QFN Thin Device Manufacturing

Package and Process Design Augmentation of QFN Leadframe Device

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