Trends in low-power RAM circuit technologies

System-level power optimization: techniques and tools

“…Designers have tackled memory bottlenecks following two pathways: (i) power-efficient technology and circuit design; (ii) advanced memory architectures that overcome the scalability limitation of flat memory. Technology and circuit design are outside the scope of this survey, the interested reader is referred to the survey by Itoh et al [1995]). We focus on memory architectures.…”

The energy complexity of register files

“…Here and in the following the value of Wpass;r is chosen in such a way that the bit line signal sufficient for sensing Vsense can be developed in at least T period 4 time, where T period is a typical CPU clocking period for a given technology level. C metal is the metal word line capacitance per unit length, and W cell is the cell width.…”

“…There is, however, a limitation on how short the word line activation pulse can be. We assume that for robustness reasons, the word line activation pulse cannot be made any shorter than T period 4 , where T period is the CPU clocking period. If bit lines are so short that the signal Vsense can be developed in a shorter period, then weaker cell transistors should be used to avoid energy waste, or a word line swing control circuitry can be used, as in [5].…”

“…There are three components to the Vsense: offset voltage due to transistor parameter mismatches, capacitive asymmetry and the coupling noise. To be specific, we assume that the cross-coupled latch-type SA is used, because it is both energy efficient and fast [4]. In [11] we show that the minimum sensing signal for this kind of SA can be estimated as Vsense = 150mV , of which a 60mV component is assumed to scale down with V dd , and a 90mV is assumed not to scale.…”

Power efficient data cache designs

“…al. [8] studied the effect of reducing supply voltage and increasing threshold voltage in order to reduce both dynamic and static power dissipation in caches.…”