The energy complexity of register files

Zyuban,; Kogge,

doi:10.1109/lpe.1998.708207

Cited by 23 publications

(36 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Many recent papers have proposed mechanisms to reduce the number of the ports by means of modifying the register file architecture, such as [8] [9] [10] [11]. A reduced number of ports may be more efficient both in terms of energy and access time, which can improve performance.…”

Section: Related Workmentioning

confidence: 99%

An Optimized Front-End Physical Register File with Banking and Writeback Filtering

Pericàs

González

Cristal

et al. 2005

Power-Aware Computer Systems

View full text Add to dashboard Cite

In recent years, processor manufacturers have converged on two types of register file architectures. Both IBM with its POWER series and Intel with its Pentium series are using a central storage for all in-flight values, which offers a high performance potential. AMD, on the other hand, uses an optimized implementation of the Future File for its line of Opteron processors. Both approaches have limitations that may preclude there application in future processor implementations. The centralized register file scales poorly in terms of power-performance. The Future File may be limited by the requirement of distributed reservation stations and by the branch misprediction recovery scheme.This paper proposes to give processor designer teams another choice by combining a traditional future file architecture with the concept of a central physical register file. This new register file is used in the "front end" in combination with value storage in the instruction queue. Further, it is shown that, contrary to what happens with a centralized R10k-like architecture, the proposed architecture can use banking that scales well with the size of structures in the processor. Only a 0.3% IPC degradation was observed when using this technique. The energy savings due to banking are fully utilized in our proposal. Further, the implementation is shown to integrate well with a technique to early release short lived values that we call writeback filtering. Overall, the resulting energy delay product is lower than in previous proposals.

show abstract

Section: Related Workmentioning

confidence: 99%

An Optimized Front-End Physical Register File with Banking and Writeback Filtering

Pericàs

González

Cristal

et al. 2005

Power-Aware Computer Systems

View full text Add to dashboard Cite

show abstract

“…Previous study [1] shows that register file can be responsible for about 25% of total processor's power consumption. And the register file of Alpha 21464 occupies over five times the area of the 64 KB primary data cache [2].…”

Section: Introductionmentioning

confidence: 99%

A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS

Han

Zhang

et al. 2012

IEICE Electron. Express

View full text Add to dashboard Cite

This paper details the design of a 64 × 32 bit 4-read 2-write register file in TSMC 65 nm LP process. The register file avoids cell banking with pseudo-differential sensing scheme. Moreover, this approach enables a fully shareable and completely symmetry cell layout which shows competitive area results. Non-full-swing technique is proposed to avoid over design and improve energy efficiency. As for the timing control module, clocked pull-down circuit cuts off a possible short-current path at high clock frequency. A prototype is implemented in TSMC 65 nm LP technology. The measured results demonstrate operation of 0.77 GHz, consuming 7.08 mW at 1.2 V, and occupying 0.018 mm 2 .

show abstract

“…Multiported register files (RFs) represent the majority of such processor modules (apart from instruction and data caches) and, as a matter of fact, they consume a portion of the power budget that can reach up 20% [3]. Zyuban et al [4] compare several RF power optimization techniques aiming at the reduction of the power consumption of such RFs and propose a model for the RF energy consumption in each clock cycle that is a weighted sum of the energy of a read and write operation (1) where is the RF energy consumption during clock cycle , is the number of write (read) accesses to the RF during clock cycle , and is the energy consumption per write (read) access.…”

Section: Introductionmentioning

confidence: 99%

“…While various techniques do exist for the reduction of the circuit-level parameters (see [4] for a comprehensive overview), software level parameters have not yet been directly addressed in the low-power literature.…”

Section: Introductionmentioning

confidence: 99%

Low-power data forwarding for VLIW embedded architectures

Sami

Sciuto

Silvano³

et al. 2002

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

Abstract-In this paper, we propose a low-power approach to the design of embedded very long instruction word (VLIW) processor architectures based on the forwarding (or bypassing) hardware, which provides operands from interstage pipeline registers directly to the inputs of the function units. The power optimization technique exploits the forwarding paths to avoid the power cost of writing/reading short-lived variables to/from the register file (RF). Such optimization is justified by the fact that, in application-specific embedded systems, a significant number of variables are short-lived, that is, their liveness (from first definition to last use) spans only few instructions. Values of short-lived variables can thus be accessed directly through the forwarding registers, avoiding writeback to the RF by the producer instruction and successive read from the RF by the consumer instruction. The decision concerning the enabling of the RF writeback phase is taken at compile time by the compiler static scheduling algorithm. This approach implies a minimal overhead on the complexity of the processor control logic and, thus, no critical path increase. The application of the proposed solution to a VLIW embedded core has shown an average RF power saving of 7.8% with respect to the unoptimized approach on the given set of target benchmarks (patent pending owned by ST Microelectronics).Index Terms-Low-power design, microprocessors, VLSI design.

show abstract

The energy complexity of register files

Abstract: Register files (RF)

Cited by 23 publications

References 7 publications

An Optimized Front-End Physical Register File with Banking and Writeback Filtering

An Optimized Front-End Physical Register File with Banking and Writeback Filtering

A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS

Low-power data forwarding for VLIW embedded architectures

Contact Info

Product

Resources

About