Trends and challenges in LDPC hardware decoders

Baas, Bevan M.

doi:10.1109/acssc.2009.5469947

Cited by 11 publications

(5 citation statements)

References 40 publications

(44 reference statements)

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“…In general, most of the partial-parallel decoders have lower decoding throughput and higher energy dissipation than the full-parallel decoders. However, the full-parallel decoders have much larger silicon area than the partial-parallel decoders [57].…”

Section: Hardware Design For Ldpc Codesmentioning

confidence: 99%

Fast Decoding and Hardware Design for Binary-Input Compressive Sensing

Wang

Shi

et al. 2012

IEEE J. Emerg. Sel. Topics Circuits Syst.

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Binary-input compressive sensing (BiCS) has recently been applied to wireless communications as a modulated coding scheme for seamless rate adaptation. Different from conventional channel codes which generate binary symbols with logical-OR (XOR) operations, BiCS generates multilevel symbols through weighted sum operation. Although BiCS can be decoded by message passing, it needs to compute the convolution of probability functions in each iteration. The high decoding complexity has prevented the technique from being applied to practical use. In this paper, we propose a fast BiCS decoding algorithm and its corresponding partial-parallel hardware design. In this algorithm, we first build lookup tables to solve the computationally intensive problem of convolution. Through these tables, we successfully convert the convolution of probabilities into the polynomial of some exponential terms. This key step allows us to use log-likelihood ratio as message in message passing decoding and a fast algorithm is developed by approximate computing. We further design a partial-parallel hardware decoder. To avoid memory collision, we propose a multilevel cyclic-shift approach to generate the CS measurement matrix. We design horizontal unit processors with the proposed tables for iterative computing. Our analyses show that the proposed fast algorithm can reduce multiplications by nearly 90%. The decoding speed of our field-programmable gate array design reaches the range of communication rate in modern wireless networks.Index Terms-Compressive sensing (CS), fast decoding, message passing, random projection codes, wireless rate adaptation.

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Section: Hardware Design For Ldpc Codesmentioning

confidence: 99%

Fast Decoding and Hardware Design for Binary-Input Compressive Sensing

Wang

Shi

et al. 2012

IEEE J. Emerg. Sel. Topics Circuits Syst.

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“…, P. In the Tanner focus on general Quasi-Cyclic LDPC codes. The Quasi-Cyclic LDPC codes is getting from special representation of a little base network is increased by restoration each vertex in by a circulate change of fundamental corner to corner Z × Z network, so as to get the absolute LDPC structure S. In most of the practical applications we are suggested to QC_LDPC codes because of their extraordinary user and hardware friendly type, a few models [14] [15].Even though we are applying on irregular LDPC codes ,the regular LDPC codes are also suitable for regular bit flipping decoders, in this design to standard = 3 and = 4 LDPC codes. For each and every decoding iteration, variable node value will be changed based on iterative update method this is defined as BF decoder.…”

Section: Characterization and Investgation Of The Pgdbfmentioning

confidence: 99%

Implementation of Low density Parity Check system using Probabilistic Gradient Descent Bit Flipping Decoder

Varri¹,

Vignesh²,

Panigrahy³

et al. 2019

IJITEE

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This paper represents the concept of hard decision decoder in which PGDBF is suitable decoder for the basic model of hard-choice decoder as long as low-density parity check code (LDPC) which is increase the error correction. This design introduced dynamic architecture which reduce the capability of random disarrangement of the PGDBF. The design is working on the Short Random Sequence (SRS) that is replica cover on the PGDBF decoding guidelines. In each iteration flipping number of bits these are focusing on improvement in performance and decoding delay. The best SRS is essential to manage the wellknown decoding achievement of PGDBF, we introduced two kind of access with same hardware categories, but various LDPC codes are perform different behaviors. In this design we are modifying small hardware decoding unit for obtaining a good decoding explanation for present and further purpose.

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“…2 Throughput is computed based on the maximum latency reported. 3 Power numbers are for = 6, Method 2. 10GBASE-T required throughput is met.)…”

Section: Comparison With Othersmentioning

confidence: 99%

“…Local and cellular wireless communication throughputs are expected to increase to hundreds of Mbps and even beyond 1 Gbps [1][2][3]. With this increased growth for bandwidth comes larger systems integration complexity and higher energy consumption per packet.…”

Section: Introductionmentioning

confidence: 99%

LDPC Decoder with an Adaptive Wordwidth Datapath for Energy and BER Co-Optimization

Shirani-Mehr

Baas

2013

VLSI Design

Self Cite

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An energy efficient low-density parity-check (LDPC) decoder using an adaptive wordwidth datapath is presented. The decoder switches between a Normal Mode and a reduced wordwidth Low Power Mode. Signal toggling is reduced as variable node processing inputs change in fewer bits. The duration of time that the decoder stays in a given mode is optimized for power and BER requirements and the received SNR. The paper explores different Low Power Mode algorithms to reduce the wordwidth and their implementations. Analysis of the BER performance and power consumption from fixed-point numerical and post-layout power simulations, respectively, is presented for a full parallel 10GBASE-T LDPC decoder in 65 nm CMOS. A 5.10 mm 2 low power decoder implementation achieves 85.7 Gbps while operating at 185 MHz and dissipates 16.4 pJ/bit at 1.3 V with early termination. At 0.6 V the decoder throughput is 9.3 Gbps (greater than 6.4 Gbps required for 10GBASE-T) while dissipating an average power of 31 mW. This is 4.6× lower than the state of the art reported power with an SNR loss of 0.35 dB at BER = 10 −7 .

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Trends and challenges in LDPC hardware decoders

Cited by 11 publications

References 40 publications

Fast Decoding and Hardware Design for Binary-Input Compressive Sensing

Fast Decoding and Hardware Design for Binary-Input Compressive Sensing

Implementation of Low density Parity Check system using Probabilistic Gradient Descent Bit Flipping Decoder

LDPC Decoder with an Adaptive Wordwidth Datapath for Energy and BER Co-Optimization

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