TRaX: A Multicore Hardware Architecture for Real-Time Ray Tracing

Spjut, Josef; Kensler, Andrew; Kopta, Daniel; Brunvand, Erik

doi:10.1109/tcad.2009.2028981

Cited by 36 publications

(20 citation statements)

References 39 publications

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“…To address this, we adapted the throughput metrics from the FPGA implementations to a clock frequency of 500 MHz in accordance with assumptions made in existing research [46][47][48]. Since 500 MHz is significantly lower than the clock frequencies of modern GPUs, we, therefore, derive a conservative estimate of throughput.…”

Section: Methodsmentioning

confidence: 99%

A hybrid fixed-function and microprocessor solution for high-throughput broad-phase collision detection

Woulfe

Manzke

2016

J Embedded Systems

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We present a hybrid system spanning a fixed-function microarchitecture and a general-purpose microprocessor, designed to amplify the throughput and decrease the power dissipation of collision detection relative to what can be achieved using CPUs or GPUs alone. The primary component is one of the two novel microarchitectures designed to perform the principal elements of broad-phase collision detection. Both microarchitectures consist of pipelines comprising a plurality of memories, which rearrange the input into a format that maximises parallelism and bandwidth. The two microarchitectures are combined with the remainder of the system through an original method for sharing data between a ray tracer and the collision-detection microarchitectures to minimise data structure construction costs. We effectively demonstrate our system using several benchmarks of varying object counts. These benchmarks reveal that, for over one million objects, our design achieves an acceleration of 812× relative to a CPU and an acceleration of 161× relative to a GPU. We also achieve energy efficiencies that enable the mitigation of silicon power-density challenges, while making the design amenable to both mobile and wearable computing devices.

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Section: Methodsmentioning

confidence: 99%

A hybrid fixed-function and microprocessor solution for high-throughput broad-phase collision detection

Woulfe

Manzke

2016

J Embedded Systems

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“…We start with a parallel decoupled architecture called TRaX because it is designed specifically for ray tracing [Spjut et al 2009], and because it is publicly available with a cycle-accurate simulator and LLVM-based compiler that we can modify for our own architectural evaluation [HWRT 2012]. We use this architecture as a starting point because we also believe that the MIMD execution model is better suited to ray tracing than the SIMD execution of traditional GPUs [Kopta et al 2008;Kopta et al 2010].…”

Section: Streaming Treelet Ray Tracing Architecture (Strata)mentioning

confidence: 99%

“…TRaX TM architecture with 32 lightweight cores and shared cache and compute resources Potential TRaX chip organization with multiple TMs sharing L2 caches Figure 1: Overall TRaX Thread Multiprocessor (TM) and multi-TM chip organization [Spjut et al 2009]. …”

Section: Streaming Treelet Ray Tracing Architecture (Strata)mentioning

confidence: 99%

“…[Wald et al 2001;Dmitriev et al 2004;Reshetov et al 2005;Wald et al 2008;Bigler et al 2006]), but ray tracing's divergent branching and irregular memory access patterns suggest that an alternate approach may be beneficial. Many have argued that a more decoupled parallel approach makes more sense for ray tracing [Govindaraju et al 2008;Seiler et al 2008;Spjut et al 2009;Kelm et al 2009;Kopta et al 2010]. In these cases, researchers opt for a Multiple Instruction, Multiple Data (MIMD), or Single Program, Multiple Data (SPMD) style of execution which reduces the requirement of collecting and sorting rays into bundles suitable for SIMD processing.…”

Section: Introductionmentioning

confidence: 99%

“…Architectural approaches for high-performance ray tracing have mostly involved the design and evaluation of non-SIMD parallel approaches that are better suited to the run-time branching behavior of ray tracing than wide SIMD processing [Govindaraju et al 2008;Seiler et al 2008;Spjut et al 2009;Kelm et al 2009;Kopta et al 2010]. These efforts can mostly be characterized as lightweight general purpose cores with relatively simple memory systems that support the simple sharing model of the parallel ray tracing algorithm.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

An energy and bandwidth efficient ray tracing architecture

Kopta

Shkurko

Spjut

et al. 2013

Proceedings of the 5th High-Performance Graphics Conference

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We propose two hardware mechanisms to decrease energy consumption on massively parallel graphics processors for ray tracing while keeping performance high. First, we use a streaming data model and configure part of the L2 cache into a ray stream memory to enable efficient data processing through ray reordering. This increases the L1 hit rate and reduces off-chip memory accesses substantially. Second, we employ reconfigurable specialpurpose pipelines than are constructed dynamically under program control. These pipelines use shared execution units (XUs) that can be configured to support the common compute kernels that are the foundation of the ray tracing algorithm, such as acceleration structure traversal and triangle intersection. This reduces the overhead incurred by memory and register accesses. These two synergistic features yield a ray tracing architecture that significantly reduces both power consumption and off-chip memory traffic when compared to a more traditional cache only approach.

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Caching architecture for flexible FPGA ray tracing platform

Collinson

Sinnen

2017

Journal of Parallel and Distributed Computing

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TRaX: A Multicore Hardware Architecture for Real-Time Ray Tracing

Cited by 36 publications

References 39 publications

A hybrid fixed-function and microprocessor solution for high-throughput broad-phase collision detection

A hybrid fixed-function and microprocessor solution for high-throughput broad-phase collision detection

An energy and bandwidth efficient ray tracing architecture

Caching architecture for flexible FPGA ray tracing platform

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