An energy and bandwidth efficient ray tracing architecture

Abstract

We propose two hardware mechanisms to decrease energy consumption on massively parallel graphics processors for ray tracing while keeping performance high. First, we use a streaming data model and configure part of the L2 cache into a ray stream memory to enable efficient data processing through ray reordering. This increases the L1 hit rate and reduces off-chip memory accesses substantially. Second, we employ reconfigurable specialpurpose pipelines than are constructed dynamically under program control. These pipelines use shared execution units (XUs) that can be configured to support the common compute kernels that are the foundation of the ray tracing algorithm, such as acceleration structure traversal and triangle intersection. This reduces the overhead incurred by memory and register accesses. These two synergistic features yield a ray tracing architecture that significantly reduces both power consumption and off-chip memory traffic when compared to a more traditional cache only approach.

Examination of the Nvidia RTX

“…The TRaX architecture [16] implements a different solutionmany identical cores consisting of simple thread processors. It can be viewed as general pur-pose architecture and is used in other papers to simu-late their hardware [7]. In the ray-tracing application TRaX accelerates single ray performance and features MIMD execution model as opposed to groups of 4 or more rays and SIMD model in previously mentioned architectures.…”

RayCore

“…Aila and Karras [2010] propose a new hardware architecture based on NVIDIA Fermi GPUs in order to reduce memory traffic via a treeletbased approach and a stack-top cache architecture. Kopta et al [2013] improve the TRaX architecture's power efficiency by using a treelet-based approach and reconfigurable pipelines.…”

Memory Considerations for Low Energy Ray Tracing

“…Many architectural simulations, including previous incarnations of our simulator [KSS*13], focus on accurate modelling of the on‐chip systems, but use a simplified approximation for DRAM performance, such as assuming an average latency and energy for all reads and writes. USIMM is a DRAM simulator with sophisticated modelling of timing and energy characteristics for the entire DRAM system [CBS*12], and has been used by a number of simulation systems as an accurate memory model [MSC12, NCQ13].…”

“…In this case, we use the Utah Simulated Memory Module (USIMM) DRAM memory simulator which includes a detailed model of the complex timing and energy behaviour of a modern DRAM memory system [CBS*12, MSC12]. The use of this memory simulator is a significant extension of our previous simulations [KSS*13] and is described in Section . Additional improvements are possible by reducing register access, and instruction fetch and decode energy by algorithmic or architectural improvements.…”