TRAVERSAL: A Fast and Adaptive Graph-Based Placement and Routing for CGRAs

Canesche, Michael; Menezes, Marcelo M.; Carvalho, Westerley; Torres, Frank Sill; Jamieson, Peter; Nacif, José Augusto M.; Ferreira, Ricardo

doi:10.1109/tcad.2020.3025513

Cited by 19 publications

(17 citation statements)

References 32 publications

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“…A solution adopted in many cases is to let the control flow managed by a host processor. But this reduces greatly the pos- Spatial mapping [23], [30], [31] GA [19] SA [32], [33] ILP [23], [34], [35] Temporal mapping [12], [16], [26], [36]- [40] SA [22] ILP [41] B&B [42] CP [43] SAT [17] SMT [44] Binding [14], [24], [28], [45]- [47] QEA [48] SA [30], [49], [50] ILP [15], [48] Scheduling [24], [28], [36], [46], [48], [50]- [52] ILP [15], [53] sibilities to use the CGRA and increases the communication overhead, loosing sometimes the benefit of the acceleration provided by the CGRA. Another approach is to provide the CGRA with extra hardware features to support the control flow.…”

Section: B Control-flow Mappingmentioning

confidence: 99%

Twenty Years of Automated Methods for Mapping Applications on CGRA

Martin

2022

2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)

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Coarse-GrainedReconfigurable Architectures (CGRAs) emerged about 30 years ago. The very first CGRAs were programmed manually. Fortunately, some compilation approaches appeared rapidly to automate the mapping process. Numerous surveys on these architectures exist. Other surveys also gather the tools and methods, but none of them focuses on the mapping process only. This paper focuses solely on automated methods and techniques for mapping applications on CGRA and covers the last two decades of research. This paper aims at providing the terminology, the problem formulation, and a classification of existing methods. The paper ends with research challenges and trends for the future.

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Section: B Control-flow Mappingmentioning

confidence: 99%

Twenty Years of Automated Methods for Mapping Applications on CGRA

Martin

2022

2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)

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“…Estas três primeiras contribuic ¸ões foram publicadas no artigo "Traversal: A fast and adaptive graph-based placement and routing for cgras." [Canesche et al 2020]. A quarta contribuic ¸ão foi o desenvolvimento de um novo algoritmo que realiza duas travessias de complexidade polinomial nos grafos, realizando uma busca guiada e inteligente no espac ¸o de soluc ¸ões.…”

Section: Contribuic ¸õEsunclassified

“…Como o posicionamento conecta diretamente 80-90% dos vértices, o roteamento precisa lidar apenas com 10-20% das arestas, que em geral, estão próximas. Estes algoritmos foram utilizados para validar às duas abordagens de posicionamento propostas [Canesche et al 2020. Além disso, foram utilizados para validar uma nova versão de posicionamento com SA do nosso grupo de pesquisa [Carvalho et al 2020, Oliveira et al 2020.…”

Section: Contribuic ¸õEsunclassified

Algoritmos de Posicionamento e Roteamento baseados em Travessia de Grafo para Arquiteturas Reconfiguráveis de Grão Grosso (CGRA)

Canesche¹,

Ferreira²

2022

Anais Do XXXV Concurso De Teses E Dissertações (CTD 2022)

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O hardware reconfigurável é flexível, eficiente energeticamente e oferece alto desempenho para vários domínios de aplicação. Os FPGAs são a tecnologia reconfigurável mais utilizada, entretanto o mapeamento da aplicação é NP-Completo. Os CGRAs simplificam o desenvolvimento de aplicações para hardware reconfigurável e alteram a granularidade das operações do nível de bit para o nível de palavras (8-32 bits). Este trabalho apresenta avanços no estado da arte para o problema de mapeamento em CGRA propondo novos algoritmos de travessia de grafos. As soluções alcançadas são ordens de grandeza mais rápidas sem comprometer a qualidade. Os algoritmos propostos foram 91x mais rápidos com uma redução de 1.7x nos recursos de balanceamento em comparação com a abordagem com Simulated Annealing.

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“…CGRA mapping consists of two steps: Placement and Routing (P&R). We simplify a greedy placement proposed in [25] to develop an FSM-based implementation in hardware. First, we represent the graph as a spanning-tree edge list (STEL) plus a list of remained edges (RE).…”

Section: A Placementmentioning

confidence: 99%

RESHAPE: A Run-Time Dataflow Hardware-Based Mapping for CGRA Overlays

Vieira

Canesche

Bragança

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Coarse-grained reconfigurable architectures (CGRA) are a power-efficient approach for hardware accelerators. However, there are few EDA tools for CGRA. We develop hardware-based placement and routing (P&R) for fully-pipelined CGRA mapped as an FPGA overlay. The key idea is to use the available FPGA resources to replicate several mapping units, thus exploring parallel execution, area/execution time trade-offs, and achieving near-optimal mapping solutions. Furthermore, our P&R provides portability and an incremental run-time approach. In comparison to VPR and CGRA-ME tools and a time-multiplexer approach, our spatial mapping reduces the P&R execution time, and it improves the performance up to hundreds of Gops/s by using fully-pipelined architectures.

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TRAVERSAL: A Fast and Adaptive Graph-Based Placement and Routing for CGRAs

Cited by 19 publications

References 32 publications

Twenty Years of Automated Methods for Mapping Applications on CGRA

Twenty Years of Automated Methods for Mapping Applications on CGRA

Algoritmos de Posicionamento e Roteamento baseados em Travessia de Grafo para Arquiteturas Reconfiguráveis de Grão Grosso (CGRA)

RESHAPE: A Run-Time Dataflow Hardware-Based Mapping for CGRA Overlays

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