Trapping phenomena and degradation mechanisms in GaN-based power HEMTs

Meneghini, Matteo; Tajalli, Alaleh; Moens, P.; Banerjee, Abhishek; Zanoni, Enrico; Meneghesso, Gaudenzio

doi:10.1016/j.mssp.2017.10.009

Cited by 85 publications

(62 citation statements)

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“…Holes in GaN:C can easily flow towards the bottom of this layer and, especially at high temperature, towards the Si substrate. Hole generation was stronger at high temperatures (consistent with [3,11]). Contrary to structure A, the leakage current of structure B is temperature dependent.…”

Section: Vertical Leakagesupporting

confidence: 80%

Vertical Leakage in GaN-on-Si Stacks Investigated by a Buffer Decomposition Experiment

et al. 2020

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We investigated the origin of vertical leakage and breakdown in GaN-on-Si epitaxial structures. In order to understand the role of the nucleation layer, AlGaN buffer, and C-doped GaN, we designed a sequential growth experiment. Specifically, we analyzed three different structures grown on silicon substrates: AlN/Si, AlGaN/AlN/Si, C:GaN/AlGaN/AlN/Si. The results demonstrate that: (i) the AlN layer grown on silicon has a breakdown field of 3.25 MV/cm, which further decreases with temperature. This value is much lower than that of highly-crystalline AlN, and the difference can be ascribed to the high density of vertical leakage paths like V-pits or threading dislocations. (ii) the AlN/Si structures show negative charge trapping, due to the injection of electrons from silicon to deep traps in AlN. (iii) adding AlGaN on top of AlN significantly reduces the defect density, thus resulting in a more uniform sample-to-sample leakage. (iv) a substantial increase in breakdown voltage is obtained only in the C:GaN/AlGaN/AlN/Si structure, that allows it to reach V BD > 800 V.(v) remarkably, during a vertical I-V sweep, the C:GaN/AlGaN/AlN/Si stack shows evidence for positive charge trapping. Holes from C:GaN are trapped at the GaN/AlGaN interface, thus bringing a positive charge storage in the buffer. For the first time, the results summarized in this paper clarify the contribution of each buffer layer to vertical leakage and breakdown.

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Section: Vertical Leakagesupporting

confidence: 80%

Vertical Leakage in GaN-on-Si Stacks Investigated by a Buffer Decomposition Experiment

et al. 2020

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“…, [2] where N o is the peak density of states, E is the running energy value. The current relaxation due to the charge emission from such a band is described by the convolution of the current relaxation contributions from narrow energy segments of the band and can be described by:…”

Section: Experimental Methods and Data Treatmentmentioning

confidence: 99%

“…One of the most serious problems with III-Nitrides-based high electron mobility transistors (HEMTs) is the phase delay of the drain current upon pulsed change of the gate bias, so called "gate-lag". [1][2][3] This phenomenon causes increase of the switching time and long-term drift of the threshold voltage and the drain current. The generally accepted view is the gate-lag is caused by trapping of electrons flowing from the gate at high reverse voltage and subsequent capture of electrons by deep centers under the gate.…”

mentioning

confidence: 99%

“…The generally accepted view is the gate-lag is caused by trapping of electrons flowing from the gate at high reverse voltage and subsequent capture of electrons by deep centers under the gate. Both the capture and emission process from these traps can be studied by analysis of gate and drain transients as a function of pulsing conditions and temperature by using current or capacitance deep level transient spectroscopy (CDLTS or DLTS) [2][3][4][5] or by direct measurements of individual transients. 1,[6][7][8][9] These measurements provide the concentration and position of the traps involved and their capture cross sections.…”

mentioning

confidence: 99%

“…7,8 Another popular approach is to build the derivative of the relaxation curve on the logarithm of time, find the peaks in such plots, and trace the peak position variation with temperature to extract the activation energy and capture cross section of the traps. 2,3,9 The number of peaks in either approach is quite limited (typically, 2-3) in either method, 9 but the peaks are generally broad which requires invoking a large number of exponents to attain good fit in the basic method, 6 while providing no knowledge on the physical nature of broadening. Good fits can be achieved when using 2-3 extended exponents describing capture and emission in the presence of broadened barriers for capture, or by Gaussian broadening of the logarithm of relaxation time describing broadening of the discrete level into Gaussian energy bands.…”

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Gate-Lag in AlGaN/GaN High Electron Mobility Transistors: A Model of Charge Capture

Polyakov

Smirnov

Shchemerov

et al. 2017

ECS J. Solid State Sci. Technol.

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Gate and drain current transients following the application of a step/pulse reverse bias to the gate of AlGaN/GaN HEMTs can be described by a superposition of 2-3 extended exponents with characteristic times of the main process having activation energy of 0.7-0.8 eV. The drain current relaxation is a consequence of charge trapping and movement in the AlGaN barrier. A qualitative model explains this process by movement of a step of charge trapped on deep states in the barrier and movement of the step toward the interface by multiple emission/capture hops. The process is assumed to be confined to channels in AlGaN (presumably dislocations) surrounded by potential barriers, preventing effective injection of the carriers into the channels with forward bias pulses. The model qualitatively explains the often reported appearance of hole-trap-like signals in deep level studies of AlGaN/GaN HEMT structures and the persistent changes in capacitance and current of these structures occurring upon pulsing and illumination. One of the most serious problems with III-Nitrides-based high electron mobility transistors (HEMTs) is the phase delay of the drain current upon pulsed change of the gate bias, so called "gate-lag". [1][2][3] This phenomenon causes increase of the switching time and long-term drift of the threshold voltage and the drain current. The generally accepted view is the gate-lag is caused by trapping of electrons flowing from the gate at high reverse voltage and subsequent capture of electrons by deep centers under the gate. Both the capture and emission process from these traps can be studied by analysis of gate and drain transients as a function of pulsing conditions and temperature by using current or capacitance deep level transient spectroscopy (CDLTS or DLTS) 2-5 or by direct measurements of individual transients.1,6-9These measurements provide the concentration and position of the traps involved and their capture cross sections. This is complicated by the presence of multiple traps, strong non-uniform electrical and strain fields, and the contribution of the band-like states related to extended defects and to surface or interface states. As a result, the drain and gate current relaxation curves are non-exponential. A common approach is the deconvolution of the actual relaxations into a sum of independent exponential relaxations and fitting the pre-exponential coefficients to experiment.6 Various methods to improve the convergence and reproducibility of the procedure exist. 7,8 Another popular approach is to build the derivative of the relaxation curve on the logarithm of time, find the peaks in such plots, and trace the peak position variation with temperature to extract the activation energy and capture cross section of the traps.2,3,9 The number of peaks in either approach is quite limited (typically, 2-3) in either method, 9 but the peaks are generally broad which requires invoking a large number of exponents to attain good fit in the basic method, 6 while providing no knowledge on the physical nature o...

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Low On‐Resistance and Low Trapping Effects in 1200 V Superlattice GaN‐on‐Silicon Heterostructures

Kabouche

Abid

Püsche³

et al. 2019

Physica Status Solidi (a)

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We report on the development of GaN-on-silicon heterostructures targeting 1200 V power applications. In particular, it is shown that the insertion of superlattices (SL) into the buffer layers allows pushing the vertical breakdown voltage above 1200 V without generating additional trapping effects as compared to a more standard optimized step-graded AlGaN-based epi-structure using a similar total buffer thickness. DC characterizations of fabricated transistors by means of back-gating measurements reflect both the enhancement of the breakdown voltage and the low trapping effects up to 1200 V. These results show that a proper buffer optimization along with the insertion of SL pave the way to GaN-on-silicon lateral power transistors operating at 1200 V with low on-resistance and low trapping effects.

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Trapping phenomena and degradation mechanisms in GaN-based power HEMTs

Cited by 85 publications

References 20 publications

Vertical Leakage in GaN-on-Si Stacks Investigated by a Buffer Decomposition Experiment

Vertical Leakage in GaN-on-Si Stacks Investigated by a Buffer Decomposition Experiment

Gate-Lag in AlGaN/GaN High Electron Mobility Transistors: A Model of Charge Capture

Low On‐Resistance and Low Trapping Effects in 1200 V Superlattice GaN‐on‐Silicon Heterostructures

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