Transition-Time-Relation based capture-safety checking for at-speed scan test generation

Abstract

Excessive capture power in at-speed scan testing may cause timing failures, resulting in test-induced yield loss. This has made capture-safety checking mandatory for test vectors. This paper presents a novel metric, called the TTR (Transition-Time-Relation-based) metric, which takes transition time relations into consideration in capture-safety checking. Capture-safety checking with the TTR metric greatly improves the accuracy of test vector sign-off and lowcapture-power test generation.

A layout-aware x-filling approach for dynamic power supply noise reduction in at-speed scan testing

“…Authors in [17], propose a method to reduce peak power supply noise during scan chain shifting by using a partitioning technique to reduce the flip-flop density belonging to the same test clock. A new metric which considers Transition Time Relation (TTR) is proposed in [18] for capture-safety checking. TTR metric, take the temporal correlation by considering transitions that only occur earlier than (not later than) any transition at each on path node.…”

A novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuits

“…Particularly in the testing of high-speed devices, even a slightly increased delay due to excessive IR-drop (launchinduced IR-drop) may cause capture malfunction, resulting in test-induced yield loss [1]. In order to avoid capture malfunction, various techniques have been proposed for reducing capture power, based on such approaches as DFT, ATPG, and test vector modification [4][5][6][7][8][9][10][11][12][13]. However, even after capture power reduction, some test vectors may still cause capture malfunction.…”

“…Several methods for capture-safety checking [8][9][10][11][12][13][14][15][16] have previously been proposed. So far, only the capture-safety checking method proposed in [13] takes transition time relations among logic gates into consideration. Earlier transitions of logic gates cause excessive IR-drop at other logic gates that have later transitions.…”

“…Earlier transitions of logic gates cause excessive IR-drop at other logic gates that have later transitions. Although method [13] can achieve more accurate results than the other methods, it does not consider transition time relations among more than one clock domain.…”

“…When multiple clock domains are simultaneously tested, there are certain differences in the clock edge arrival times of flip-flops in different domains [18]. Therefore, if more than one domain captures the responses in a short period of time, transition time relations must be considered among different domains as well as transition time relation capture-safety checking [13]. Obviously, the impact of IRdrop varies depending on the clock edge arrival time at each clock domain.…”