Transition time modeling in deep submicron CMOS

Maurine, Philippe; Rezzoug, M.; Azémard, Nadine; Auvergne, D.

doi:10.1109/tcad.2002.804088

Cited by 44 publications

(50 citation statements)

References 21 publications

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“…Since the model proposed in [12][13][14] is intensively used all along this paper, we sum-up below its main characteristics considering for simplicity only the case of falling output edges.…”

Section: Ii-analytical Timing Modelmentioning

confidence: 99%

Temperature and Voltage Aware Timing Analysis: Application to Voltage Drops

Lasbouygues¹,

Wilson²,

Azemard³

et al. 2007

2007 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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In the nanometer era, the physical verification of CMOS digital circuit becomes a complex task. Designers must account of new factors that impose a significant change in validation methods. One of these major changes in timing verification to handle process variation lies in the progressive development of statistical static timing engines. However the statistical approach cannot capture accurately the deterministic variations of both the voltage and temperature variations. Therefore, we define a novel method, based on non-linear derating coefficients, to account of these environmental variations. Based on temperature and voltage drop CAD tool reports, this method allows computing the delay of logical paths considering more realistic operating conditions for each cell. Application is given to the analysis of voltage drop effects on timings.

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Section: Ii-analytical Timing Modelmentioning

confidence: 99%

Temperature and Voltage Aware Timing Analysis: Application to Voltage Drops

Lasbouygues¹,

Wilson²,

Azemard³

et al. 2007

2007 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

Self Cite

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show abstract

“…To evaluate this validity domain, the modelling of the switching current waveform of CMOS dual rail gate is of prime importance. Considering that any single rail gate can be reduced to an equivalent inverter [11], let us model any dual rail cell by two inverters as illustrated by Fig.2. With such a reduction procedure, the modelling of the switching current waveform of dual rail gates comes down to the modelling of the switching current waveform of basic cmos inverters.…”

Section: Dpa and The Dual Rail Countermeasurementioning

confidence: 99%

“…With such a reduction procedure, the modelling of the switching current waveform of dual rail gates comes down to the modelling of the switching current waveform of basic cmos inverters. A great effort has been dedicated to the modelling of the inverter switching process [11,12]. For typical loading and controlling conditions (Fast input ramps [11]), the switching current waveform of a CMOS gate can be modelled by a piece wise linear function as illustrated by Fig.3.…”

Section: Dpa and The Dual Rail Countermeasurementioning

confidence: 99%

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Security evaluation of dual rail logic against DPA attacks

Razafindraibe

Maurine

Robert

et al. 2006

2006 IFIP International Conference on Very Large Scale Integration

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“…Other attempts use analytical solutions for fast input transitions and add correction terms with empirical optimized parameters to cover the slow input transition case 9 or map the short-circuit current contribution to an additional output capacitance. 10,11 In this paper, an analytical approximation for the timing and power consumption is proposed which is based on few constant (for one technology) parameters. The paper is organized in the following way: In Section 2, various mathematical models for MOS transistors are compared with respect to complexity and accuracy.…”

Section: Introductionmentioning

confidence: 99%

Timing and power model for CMOS inverters

Geibler

Pfleiderer

2003

SPIE Proceedings

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Nowadays, the delay, the output transition time and the short circuit power consumption of CMOS gates depend on the load capacitance and the input transition time. In currently used technology libraries, table models with 25 or more samples are used for calculating by interpolation each of these three variables. Previous work deriving analytical models are based on neglecting the short circuit current or approximating currents as piecewise linear. In the beginning of this paper, different mathematical models describing the transistor current are compared with respect to the accuracy of a numerical calculated output waveform. The results show that Sakurai's alphaPower Model with linear equation in the linear region and exponent α = 1 serves as a well-fitting model for the underlying 0.35 µm technology. Based on this transistor model and the assumption of a linear rising input, the differential equation of the output voltage, including both transistor currents and the capacitive load, has to be solved. Splitting the solution into regions, an approximate solution can be derived for the case that the PMOS transistor is working in linear and the NMOS in saturation condition. The rather complex calculation of the point where the PMOS transistor switches from linear to saturation region can be simplified by using curve fitting techniques. The required curve parameters depend on technology constants as in MM9 and the quotient w n /w p . Consequently, one set of parameters allows the analysis of a wide range of inverters as long as w n /w p is kept constant. The accuracy of the results for the delay are typically within 10%, those for output transition time and power consumption within 5% compared to SPICE simulation.

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Transition time modeling in deep submicron CMOS

Cited by 44 publications

References 21 publications

Temperature and Voltage Aware Timing Analysis: Application to Voltage Drops

Temperature and Voltage Aware Timing Analysis: Application to Voltage Drops

Security evaluation of dual rail logic against DPA attacks

Timing and power model for CMOS inverters

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