Transition Detector-Based Radiation-Hardened Latch for Both Single- and Multiple-Node Upsets

Tajima, Saki; Yanagisawa, Masao; Shi, Youhua

doi:10.1109/tcsii.2019.2926498

Cited by 18 publications

(9 citation statements)

References 10 publications

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“…Therefore, in order to provide highly reliable integrated circuits, it is necessary to design storage cells that can tolerate and even recover from MNU. To provide radiation hardening capability, researchers have proposed a series of radiation-hardened circuit structures [8][9][10][11][12][13][14][15][16][17][18][19][20][21][22]. Some of them use time redundancy, e.g., using delay elements as error-filterable components [8], some use pulse detection technology, such as that in [9], and some use space redundancy, e.g., introducing redundant storage nodes and/or triple-moduleredundancy (TMR) along with voting circuits [10][11][12][13][14].…”

Section: Introductionmentioning

confidence: 99%

Design of a Novel Latch with Quadruple-Node-Upset Recovery for Harsh Radiation Hardness

Yan,

Zhou,

Wei

et al. 2023

2023 IEEE International Test Conference in Asia (ITC-Asia)

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As CMOS processes continue to shrink, nano-scale CMOS latches have become increasingly sensitive to multiplenode upset (MNU) errors caused by radiation. To tolerate MNU, a novel quadruple-node-upset (QNU) self-recoverable latch is proposed in this paper. The proposed latch is mainly constructed from six blocks of three-level C-elements (TLCEs) and six inverters. With the mutual feedback of the various TLCEs, the proposed latch can recover from any QNU. Furthermore, due to the clock gating methodology and a highspeed transmission path, the proposed latch has lower overhead in terms of power dissipation and transmission delay. Simulation results show that the proposed latch achieves high reliability with moderate overhead compared to typical existing latches.

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Section: Introductionmentioning

confidence: 99%

Design of a Novel Latch with Quadruple-Node-Upset Recovery for Harsh Radiation Hardness

Yan,

Zhou,

Wei

et al. 2023

2023 IEEE International Test Conference in Asia (ITC-Asia)

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“…Xiaoqing Wen is with the Graduate School of Computer Science and Systems Engineering, Kyushu Institute of Technology, Fukuoka 820-8502, Japan (E-mail: wen@cse.kyutech.ac.jp) have proposed many circuit components such as static random access memories (SRAMs) [10][11][12][13], flip-flops [14][15][16][17], and latches [6][7][8][9][18][19][20][21][22][23][24][25][26][27][28]. Note that this paper proposes two contributions, i.e., voter designs and latch hardening.…”

Section: Introductionmentioning

confidence: 99%

“…1) Traditional voters have large overhead and they cannot filter SET pulses. 2) Existing latches can only provide a part of TNU tolerance [18][19][20][21][22][23][24][25][26][27] (this is because, for any of them, there is at least one combination of three nodes that retain invalid values if the latch is impacted by a TNU); some of them cannot filter SET pulses [6-9, 18-19, 22, 24-28] (This is because, for any of them, an SET pulse can unfortunately propagate from the input to the output); to the best of our knowledge, none of them can provide TNUtolerance and SET-filterability simultaneously, except our proposed HITTSFL latch that is published in the conference version paper [30]. Note that some existing latches are sensitive to highimpedance state (HIS) because they use Celements (CEs) to output values [6-7, 9, 18, 29].…”

Section: Introductionmentioning

confidence: 99%

Cost-Effective and Highly Reliable Circuit-Components Design for Safety-Critical Applications

Yan

Fan

Liang

et al. 2022

IEEE Trans. Aerosp. Electron. Syst.

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With the reduction of technology nodes now reaching 2nm, circuits become increasingly susceptible to external perturbations. Thereby, soft errors, such as single-node-upset (SNU), singleevent-transient (SET), double-node-upset (DNU), and even triple-node-upset (TNU), must be considered for safety-critical applications. This paper first presents four advanced circuit components (i.e., advanced voters), that have very small overhead compared with the traditional voters. The proposed Advanced Triple-Modular-Redundancy (ATMR) and Advanced Quadruple-Modular-Redundancy (AQMR) voters only consist of four and six inverters, respectively, to provide effective tolerance against SNUs and DNUs. To further filter SETs, a Schmitt-trigger (ST) instead of an inverter at the output-level is used to construct the ATMR-ST and AQMR-ST voters. These proposed voters can also be extended to tolerate TNUs. Next, these voters are used for latch hardening, so that this paper also presents a series of voter-based latch designs, to ensure high reliability with cost-effectiveness. Simulation results demonstrate the node-upset tolerance and/or SET-filterability of the proposed voters and voter-based latches, respectively. Simulation results also demonstrate that the proposed ATMR voter can reduce delay, power, and area by 55.2%, 32.8%, and 32.2%, respectively, compared with the traditional TMR voter; the proposed so-called HITTSFL latch can reduce delay, power, and area by 78.9%, 15.8%, and 28.6%, respectively, compared with the state-ofthe-art TNU hardened latch (TNUHL).

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“…To mitigate SNUs, DNUs, TNUs, and/or SETs, by means of radiation-hardening-by-design (RHBD) approaches, many hardened storage cells such as static random access memories (SRAMs) [9][10][11][12], flip-flops [13][14][15][16], and latches [5][6][7][8][17][18][19][20][21][22][23][24][25][26][27], have been proposed. This paper focuses on latches.…”

Section: Introductionmentioning

confidence: 99%

“…1) They cannot provide complete TNU-tolerability [17][18][19][20][21][22][23][24][25][26] since there is at least one counterexample that an invalid value will be retained if any of them suffers from a TNU. 2) They cannot provide SET-filterability [5-8, 17-18, 21, 23-27] since SETs can unfortunately propagate to the output from the input for any of them.…”

Section: Introductionmentioning

confidence: 99%

HITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filterable Latch for Safety-Critical Applications

Yan

Feng

Zhao

et al. 2020

2020 57th ACM/IEEE Design Automation Conference (DAC)

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This paper proposes a cost-effective, high-impedancestate (HIS)-insensitive, triple-node-upset (TNU)-tolerant and single-event-transient (SET)-filterable latch, namely HITTSFL, to ensure high reliability with low-cost. The latch mainly comprises an output-level SET-filterable Schmitt-trigger and three inverters that make the values stored in three parallel single-node-upset (SNU)-recoverable dual-interlocked-storagecells (DICEs) converge at a common node to tolerate any possible TNU. The latch does not use C-elements to be insensitive to the HIS. Simulation results demonstrate the TNU-tolerability and SET-filterability of the proposed HITTSFL latch. Moreover, due to the use of clock-gating technologies and fewer transistors, the proposed latch can reduce delay, power, and area by 76.65%, 6.16%, and 28.55%, respectively, compared with the state-of-theart TNU hardened latch (TNUHL) that cannot filter SETs.

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Transition Detector-Based Radiation-Hardened Latch for Both Single- and Multiple-Node Upsets

Cited by 18 publications

References 10 publications

Design of a Novel Latch with Quadruple-Node-Upset Recovery for Harsh Radiation Hardness

Design of a Novel Latch with Quadruple-Node-Upset Recovery for Harsh Radiation Hardness

Cost-Effective and Highly Reliable Circuit-Components Design for Safety-Critical Applications

HITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filterable Latch for Safety-Critical Applications

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