Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint

Borah, M.; Owens, R.M.; Irwin, M.J.

doi:10.1145/224081.224111

Cited by 36 publications

(21 citation statements)

References 16 publications

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“…Methods of automating transistor sizing for timing optimization were proposed in [3,[10][11][12][13][14][15][16], but many of them focus on static CMOS circuits and technologies using multiple threshold voltages. TImed LOgic Synthesizer (TILOS) [10] presented an algorithm of iteratively sizing transistors by a certain factor in the critical path.…”

Section: Previous Workmentioning

confidence: 99%

Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations

Yelamarthi

Chen

2010

VLSI Design

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The complexity of timing optimization of high-performance circuits has been increasing rapidly in proportion to the shrinking CMOS device size and rising magnitude of process variations. Addressing these significant challenges, this paper presents a timing optimization algorithm for CMOS dynamic logic and a Path Oriented IN Time (POINT) optimization flow for mixedstatic-dynamic CMOS logic, where a design is partitioned into static and dynamic circuits. Implemented on a 64-b adder and International Symposium on Circuits and Systems (ISCAS) benchmark circuits, the POINT optimization algorithm has shown an average improvement in delay by 38% and delay uncertainty from process variations by 35% in comparison with a state-of-the-art commercial optimization tool.

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Section: Previous Workmentioning

confidence: 99%

Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations

Yelamarthi

Chen

2010

VLSI Design

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“…In many design scenarios, circuit delay is determined based on system-level considerations, and hence during optimization, one must minimize energy under user-specified timing constraints. Indeed, much of the published literature focuses on this problem, although authors have referred to it as minimizing power (calculated under a fixed clock frequency) under a given delay constraint (see for example [12] [153] [139]). To set the terminology straight, these works are minimizing energy under a delay constraint.…”

Section: Towards a Useful Guide For Making Design Trade-offsmentioning

confidence: 99%

“…In [12], the problem of transistor sizing in a static CMOS layout to minimize the capacitive plus short circuit power dissipation. It is shown that the power-optimal size for the transistors in a gate that is driving a given load, can be larger than minimum size.…”

Section: Transistor and Gate Sizingmentioning

confidence: 99%

Power minimization in IC design

Pedram

1996

ACM Trans. Des. Autom. Electron. Syst.

392

135

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Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an in-depth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing design-ers at architectural, logic and physical levels of design abstraction. It reviews some of the techniques and tools that have been proposed to overcome these difficulties and outlines the future challenges that must be met to design low power, high performance systems.

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“…[4,5,6]. Gate sizing has been utilized not only for delay optimization but also for power optimization [7,8,9,10]. The main idea of previous approaches for power reduction is to optimize the amount of capacitive load [7,8] or the amount of capacitive load and short-circuit current [9,10] based on the transition activity information obtained beforehand.…”

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confidence: 99%

A power optimization method considering glitch reduction by gate sizing

Hashimoto¹,

Onodera²,

Tamaru³

1998

Proceedings of the 1998 International Symposium on Low Power Electronics and Design - ISLPED '98

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We propose a power optimization method considering glitch reduction by gate sizing. Our method reduces not only the amount of capacitive and short-circuit power consumption but also the power dissipated by glitches which has not been exploited previously. In the optimization method, we improve the accuracy of statistical glitch estimation method and device a gate sizing algorithm that utilizes perturbations for escaping a bad local solution. The effect of our method is verified experimentally using 12 benchmark circuits with a 0.5 m standard cell library. Gate sizing reduces the number of glitch transitions by 38.2 % on average and by 63.4 % maximum. This results in the reduction of total transitions by 12.8 % on average. When the circuits are optimized for power without delay constraints, the power dissipation is reduced by 7.4 % on average and by 15.7 % maximum further from the minimum-sized circuits. ½ ÁÒØÖÓ Ù Ø ÓÒThe dynamic power dissipation, which is the dominant source of power dissipation, is directly related to the number of signal transitions in a circuit. A signal transition can be classified into two categories; a functional transition(steady-state transition) and a spurious transition(glitch). It is well known that glitches occupy a considerable amount in the signal transitions of a circuit. Reference [1] indicates that the glitch power dissipation accounts for 20% to 70%, and Ref.[2] says 7% to 43%. Also glitches are extremely sensitive to signal propagation characteristics(delay) [3]. If we properly optimize timing characteristics such that the number of glitches is minimized, and if the area(power) cost for the optimization is small, we can expect that the power cost is well overcompensated and overall power dissipation is reduced by the glitch reduction.Gate sizing is an effective method for delay optimization and many solutions are proposed such as Refs. [4,5,6]. Gate sizing has been utilized not only for delay optimization but also for power optimization [7,8,9,10]. The main idea of previous approaches for power reduction is to optimize the amount of capacitive load [7,8] or the amount of capacitive load and short-circuit current [9,10] based on the transition activity information obtained beforehand. The transition activity, however, is affected by the sizing operation, which is not considered in the optimization. Although Ref. [10] proposes to update the transition information a few times during the optimization, it is not enough to fully consider the sensitivity of glitch activity with respect to timing modification cased by a sizing operation. None of the previous approaches explicitly optimize the number of transitions for power reduction. In this paper, we propose a power optimization method considering glitch reduction by gate sizing. Our method utilizes the sensitivity for reducing power consumed by glitches.Our optimization method consists of two techniques; a statistical estimation method of glitch activities and an optimization algorithm for gate sizing. For the estimation of glitch...

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Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint

Cited by 36 publications

References 16 publications

Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations

Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations

Power minimization in IC design

A power optimization method considering glitch reduction by gate sizing

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