Transient robustness testing of silicon carbide (SiC) power MOSFETs

Abstract

This paper presents the development of a unified test set-up and experimental results of the robustness characterisation of new generation of silicon carbide (SiC) power MOSFETs. In particular, unclamped inductive switching (UIS) and short-circuit withstand capability (SC) are investigated, with the aim of assessing the actual limits of operation of the devices and highlighting the underlying physical mechanisms. An electro-thermal device model is used to support the experimental analysis and interpret the observations.

SiC power MOSFETs performance, robustness and technology maturity

“…7), indicates an important reduction of the current rating of the device, compatible with the degradation mechanism put forward previously, that is, degradation of the gate structure leading to reduction of the effective active area. The temperature estimated under these power dissipation conditions was also compatible with this interpretation [19], which also found confirmation in other studies, which reported significant variation in the gate leakage current as a consequence of short-circuit stress [20]. Finally, as voltage and temperature are further increased, the device fails catastrophically without being able to do 10 s, Fig.…”

“…MOSFETs avalanche ruggedness is typically assessed with Unclamped Inductive Switching (UIS) tests [19,22]. The typical robustness limit in Si is related to the activation of the parasitic BJT structure, which becomes more likely as temperature increases due to the significant reduction of the p-n junction forward bias voltage.…”

A Comprehensive Study on the Avalanche Breakdown Robustness of Silicon Carbide Power MOSFETs

“…However, the wider bandgap of SiC makes it highly unlikely for the activation of the parasitic BJT element during typical UIS events (i.e., with typical values of switched currents and ensuing temperature evolution). Previous publications have shown that commercially available SiC MOSFETs exhibit significant intrinsic avalanche ruggedness and could dissipate E AV above 1 J, depending on the test conditions [5][6][7]13,14]. Even though different studies have presented experimental avalanche robustness, the understanding of its failure mechanism stills remains somewhat unclear and lacking.…”

“…The rated breakdown voltage (VBR(DSS)) for these devices is 1200 V but the actual breakdown voltage (VBR(eff)) is found to be around 1800 V. As shown in [7,14], failure can occur at different EAV (up to 1 J) based on current profile and TCASE. Here, current value was chosen to align with applications in power converters.…”

Transient out-of-SOA robustness of SiC power MOSFETs

“…Increasing the value of TCASE up to 150 °C, nominal rated temperature for the devices under test, only has the effect of reducing the time it takes for the same effects to be observed, but does not modify the failure signature. However, as VDS is progressively increased, the device features a different failure signature, characterised by a noticeable reduction of its withstand capability and by catastrophic failure, without possibility of turning it off safely even for very small increments of the pulse, of the order of few tens of ns [4,5]. Fig.…”