Transient fault models and AVF estimation revisited

George, Nishant; Elks, Carl; Johnson, B.W.; Lach, John

doi:10.1109/dsn.2010.5544276

Cited by 60 publications

(57 citation statements)

References 15 publications

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“…A large area percentage of such circuits is occupied by several in-core memory arrays, typically implemented using SRAM cells. To the best our knowledge, while extensive studies have been performed on increasing the reliability of caches and register files [9], [10], there are only a few MBU studies targeting modern microprocessor modules [11], [8], [12], [13]. The reason for the absence of such studies is three-fold: In this paper, we address the aforementioned issues and we present a multiple bit error vulnerability analysis study in a complex modern microprocessor module.…”

Section: Introductionmentioning

confidence: 93%

“…Another investigation of multi-bit failure rate in advanced memories appears in [4], targeting 65nm processes. The latter study triggered the definition of a new probabilistic framework for incorporating vulnerability of memories to different fault multiplicities into AVF [12]. Finally, [8] investigates the effects of multiple non-concurrent faults on the operation of a microprocessor.…”

Section: Related Workmentioning

confidence: 99%

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Investigating the limits of AVF analysis in the presence of multiple bit errors

Maniatakos

Michael

Makris

2013

2013 IEEE 19th International on-Line Testing Symposium (IOLTS)

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We investigate the complexity and utility of performing Multiple Bit Upset (MBU) vulnerability analysis in modern microprocessors. While the Single Bit Flip (SBF) model constitutes the prevailing mechanism for capturing the effect of Single Event Upsets (SEUs) due to alpha particle or neutron strikes in semiconductors, recent radiation studies in 90nm and 65nm technology nodes demonstrate that up to 55% of such strikes result in Multiple Bit Upsets (MBUs). Consequently, the accuracy of popular vulnerability analysis methods, such as the Architecural Vulnerability Factor (AVF) and Failures In Time (FIT) rate estimates based on the SBF assumption comes into question, especially in modern microprocessors which contain a significant amount of memory elements. Towards alleviating this concern, we present an extensive infrastructure which enables MBU vulnerability analysis in modern microprocessors. Using this infrastructure and a modern microprocessor model, we perform a large scale MBU vulnerability analysis study and we report two key findings: (i) the SBF fault model overestimates vulnerability by up to 71%, as compared to a more realistic modeling and distribution of faults in the 90nm and 65nm processes, and (ii) the rank-ordered lists of critical bits, as computed through the SBF and MBU models, respectively, are very similar, as indicated by the average rank difference of a bit which is less than 1.45%.

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Section: Introductionmentioning

confidence: 93%

Section: Related Workmentioning

confidence: 99%

Investigating the limits of AVF analysis in the presence of multiple bit errors

Maniatakos

Michael

Makris

2013

2013 IEEE 19th International on-Line Testing Symposium (IOLTS)

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“…These faults are expected to increase in the future processors due to shrinking size of the transistors. A two-bit spatial multi-bit upset can manifest in two ways: horizontal or vertical [8]. Horizontal means two adjacent bits on the same word are upset.…”

Section: Multi-bit Faultsmentioning

confidence: 99%

“…al. [8] injected single and double transient faults due to single particle strike. They injected faults to the register file and to the reorder buffer by using a functional simulator (PtlSim).…”

Section: Related Workmentioning

confidence: 99%

FIMSIM: A fault injection infrastructure for microarchitectural simulators

Yalcin

Unsal

Cristal

et al. 2011

2011 IEEE 29th International Conference on Computer Design (ICCD)

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Abstract-Fault injection is a widely used approach for experiment-based dependability evaluation in which faults can be injected to the hardware, to the simulator or to the software. Simulation based fault injection is more appealing for researchers, since it can be utilized at the early design stage of the processor. As such, it enables a preliminary analysis of the correlation between the criticality of circuit level faults and their impact on applications. However, the lack of publicly available fault injectors for microarchitecture level simulators brings extra burden of designing and implementing fault injectors to the researchers who evaluate microarchitecture dependability. In this study, we present FIMSIM, to the best of our knowledge, the first publicly available fault injection simulator at the microarchitecture level. FIMSIM is a compact tool which is capable of injecting transient, permanent, intermittent and multi-bit faults. Therefore, FIMSIM provides the opportunity to comprehensively evaluate the vulnerability of different microarchitectural structures against different fault models.

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“…Other papers also report research related to evaluation of derating factors and architectural vulnerability. Additional details on this topic may be found in [6][7][8][9][10].…”

Section: Introductionmentioning

confidence: 99%

Error injection-based study of soft error propagation in AMD Bulldozer microprocessor module

Constantinescu

Butler

Weller

2012

IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012)

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Single-event upsets (SEU) and single-event transients (SET) may lead to crashes or even silent data corruption (SDC) in microprocessors. Error detection and recovery features are employed to mitigate the impact of SEU and SET. However, these features add performance, area, power, and cost overheads. As a result, designers must concentrate their efforts on protecting the most sensitive areas of the processor. Simulated error injection was used to study the propagation of the SEU-induced soft errors in the latest AMD microprocessor module, Bulldozer. This paper presents the Bulldozer architecture, error injection methodology, and experimental results. Propagation of soft errors is quantified by derating factors. Error injection is performed both at the module and unit level, derating factors and simulation times being compared. Accuracy is assessed by deriving confidence intervals of the derating factors. The experiments point out the most sensitive units of the Bulldozer module, and allow efficient implementation of the error-handling features.

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Transient fault models and AVF estimation revisited

Cited by 60 publications

References 15 publications

Investigating the limits of AVF analysis in the presence of multiple bit errors

Investigating the limits of AVF analysis in the presence of multiple bit errors

FIMSIM: A fault injection infrastructure for microarchitectural simulators

Error injection-based study of soft error propagation in AMD Bulldozer microprocessor module

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