Transforming SystemC Transaction Level Models into UPPAAL timed automata

Herber, Paula; Pockrandt, Marcel; Glesner, Sabine

doi:10.1109/memcod.2011.5970523

Cited by 23 publications

(13 citation statements)

References 8 publications

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“…The resulting model can be used to verify important properties in TCTL with the Uppaal model checker. We have published the basic approach in [HPG11] and an optimized version in [PHG11].…”

Section: Main Contributionsmentioning

confidence: 99%

“…We first presented our formalization of the TLM 2.0 communication infrastructure in [HPG11] and an enhanced formalization featuring a strongly optimized version of the payload event queue in [PHG11].…”

Section: Formal Model Of Systemc/tlmmentioning

confidence: 99%

“…Whenever the point in time for a notification is reached, the list element is processed by the fec method. Our first attempt to model the time-ordered list in Uppaal (presented in [HPG11]) by using a single timed automata and a sorted array, proved to scale poorly and drastically decreased the performance of the formal verification. The main problem was the ordering of the list elements, which introduced a severe overhead.…”

Section: Time-ordered Listmentioning

confidence: 99%

“…This includes the basic transformation rules for SystemC presented by Herber et al as well as our transformation rules for the TLM standard presented in [HPG11] and [PHG11]. We extended this implementation for our memory representation during the master thesis of Rolf Schröder [Sch13].…”

Section: Sc2uppaalmentioning

confidence: 99%

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Model Checking Memory-Related Properties of Hardware/Software Co-designs

Pockrandt

Herber

Klös

et al. 2013

IFIP Advances in Information and Communication Technology

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Hardware/software codesign enables the integrated development of hardware and software in a single design language. In combination with transaction level modeling, it can be used to efficiently model complex systems on different levels of abstraction. As such systems are often used in safety-critical applications, the correctness is crucial to prevent high financial losses or casualties. Especially memory-related errors can cause severe problems as they either result in deadlocks, runtime-errors or undefined system behavior. Although HW/SW codesign usually provides means for testing and simulation during the whole development process, these techniques are incomplete and can never ensure the absence of errors. In contrast, formal verification techniques like model checking can be used to guarantee the correctness of a design. Although there exist several approaches for the formal verification of HW/SW codesigns, memory-related constructs and operations are only insufficiently considered.In this thesis, we present an approach for model checking of memoryrelated properties on digital HW/SW systems. To this end, we focus on the system level description language SystemC, the de facto standard for HW/SW codesign. To support transaction level modeling, we additionally take the widely used SystemC transaction level modeling standard (TLM) into account. The main idea of our approach is to provide a formal semantics for the most relevant parts of the TLM standard and a formal memory model, which captures all relevant memory-related constructs and operations. We combine these with an already existing formalization of the basic SystemC constructs and provide transformation rules to enable the fully automatic transformation of SystemC/TLM designs into semantically equivalent Uppaal timed automata models. On the resulting model, we use the Uppaal model checker to verify important properties, including memory-related properties, timing, liveness and safety properties. To ease this verification, we automatically generate a set of verification properties, which can be used to ensure the absence of many common errors in a given design. This includes memory-related errors like null pointer accesses and array out of bounds accesses on a given design as well as the absence of assertion violations.If a property is violated, the Uppaal model checker generates a counterexample. As our formal semantics for SystemC/TLM is structure-preserving, this counterexample can easily be transferred back to the SystemC/TLM code manually and thereby allows for the localization of detected errors. To enhance the applicability of our approach for complex designs, we provide a set of optimization techniques. These are used to reduce the semantic state space and, thus, yield a better verification performance.We have implemented our transformation and our optimization techniques in a toolchain, which can be applied to SystemC/TLM designs fully automatically. We demonstrate both, the verification performance and the errordetection capabilities of ...

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“…The resulting model can be used to verify important properties in TCTL with the Uppaal model checker. We have published the basic approach in [HPG11] and an optimized version in [PHG11].…”

Section: Main Contributionsmentioning

confidence: 99%

Section: Formal Model Of Systemc/tlmmentioning

confidence: 99%

Section: Time-ordered Listmentioning

confidence: 99%

Section: Sc2uppaalmentioning

confidence: 99%

See 2 more Smart Citations

Model Checking Memory-Related Properties of Hardware/Software Co-designs

Pockrandt

Herber

Klös

et al. 2013

IFIP Advances in Information and Communication Technology

Self Cite

View full text Add to dashboard Cite

show abstract

“…We can see that many researchers convert the semantics or behavioral model of the SLDL into another well-defined representation and make use of existing tools to validate the extracted properties. In [3] and [4], a method to generate a state machine from SystemC and using existing tools for test case generation is proposed; in [5] and [6], a SystemC design is mapped into semantics of UPPAAL time automata and the resulting model can be checked by using UPPAAL model checker; [7] proposed an approach to translate SystemC models into a Petri-net based representation for embedded systems(PRES+) which can then be used for model checking. In [8], a SystemC design is represented in the form of predictive synchronization dependency graph (PSDG) and extended Petri Net, and an approach combining simulation and static analysis to detect deadlocks is proposed.…”

Section: Related Workmentioning

confidence: 99%

Formal Deadlock Analysis of SpecC Models Using Satisfiability Modulo Theories

Chang

Dömer

2013

IFIP Advances in Information and Communication Technology

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Abstract. For a system-on-chip design which may be composed of multiple processing elements running in parallel, improper execution order and communication assignment may lead to problematic consequences, and one of the consequences could be deadlock. In this paper, we propose an approach to abstracting SpecC-based system models for formal analysis using satisfiability modulo theories (SMT). Based on the language execution semantics, our approach abstracts the timing relations between the time intervals of the behaviors in the design. We then use a SMT solver to check if there are any conflicts among those timing relations. If a conflict is detected, our tool will read the unsatisfiable model generated by the SMT solver and report the cause of the conflict to the user. We demonstrate our approach on a JPEG encoder design model.

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