Transforming gate misalignment into a unique opportunity to facilitate steep switching in junctionless nanotransistors

Abstract

In this work, we examine the feasibility of triggering impact ionisation at sub-bandgap voltages through optimal utilisation of structural non-ideality induced electric field redistribution in the semiconductor film for an energy efficient steep switching junctionless (JL) transistor. While misalignment between front and back gates is often considered as a disadvantage due to loss of gate controllability, the work highlights its usefulness and applicability in nanoscale devices to engineer the electric field to enhance the product of current density (J) and electric field (E) and activate impact ionisation at sub-bandgap applied voltages. Results show that intentionally misaligned gates in silicon and germanium based JL devices exhibit an inclined conduction channel and achieve a nearly ideal value of steep subthreshold swing (∼ 1 mV decade) at room temperature. The work provides new viewpoints to realise energy efficient JL devices through the sharp increase of drain current from off-state to on-state achieved due to intentional misalignment between front and back gates.

Hysteresis free negative total gate capacitance in junctionless transistors

“…The results reported in the literature [20][21][22] demonstrate the potential of a simple device architecture with the same type of dopants in the source/drain and channel regions for achieving S-swing<60 mV/decade at relatively lower applied biases in comparison to their inversion mode counterparts [20]. The previously reported work [23][24][25][26][27] on II in the JL transistor has focused on the understanding of floating body effects, steep S-swing and occurrence of hysteresis [20,23,24]. The problem associated with II phenomenon in JL transistor is the occurrence of hysteresis, i.e.…”

Impact of core thickness and gate misalignment on rectangular core–shell based double gate junctionless field effect transistor

“…Further, the optimization of rectangular core thickness at different shell thicknesses to obtain best performance parameters is also carried out in this section. Also, it is known that the misalignment of top and bottom gate during the fabrication of FET is the most common possibility [32,33]. Due to gate misalignment, the control of gate on the carriers reduces and thus affects the device performance.…”

Study of digital/analog performance parameters of misaligned gate recessed double gate junctionless field-effect-transistor for circuit level application

“…The fabrication of DG structure with perfectly aligned gate electrodes has been a critical issue in sub-100 nm regimes [18][19][20][21][22]. The effect of gate misalignment on the subthreshold characteristics and various analog/RF parameters of various junction-based and junctionless DG FETs has been presented in the literature [23][24][25][26][27][28][29][30][31][32]. It has been shown that misalignment primarily impacts the electrostatic strength of gate electrodes in the channel region which results in degraded subthreshold performance [23][24][25][26][27][28][29].…”

“…However, it has been noticed that most of these studies focusing on the effect of gate misalignment have been limited to investigating the subthreshold characteristics and/or analog/radio frequency (RF) performance parameters for different junctionless and junction-based FET structures [23][24][25][26][27][28][29][30][31][32]. To the best of our knowledge, the impact of gate misalignment in digital/analog circuits has yet not been studied extensively.…”