Tradeoffs in Time-to-Digital Converter Architectures for Harsh Radiation Environments

Abstract

Performance degradation of standard time-to-digital converters is inevitable due to the effects of ionising radiation. In this article, the trade-offs of different mitigation techniques for time-to-digital converter architectures are presented. As the effect of radiation is challenging for such high-performance circuits in the state of the art technologies, architectures that can compensate for radiation effects have become a necessity for TDCs to operate in these harsh radiation environments. By looking into the functionality of different architectures focusing on improving radiation tolerance, the main weak and strong points of different time-to-digital converter architectures, including the compensation circuitry, are described. Possible solutions to those weak points are presented.Index Terms-Delay locked loop (DLL), enclosed layout transistor (ELT), gated ring oscillator (GRO), multi-stage noise shaping (MASH), phase locked loop (PLL), radiation hardened, time-to-digital converter (TDC), total ionising dose (TID), triple modular redundancy (TMR)

5.7 ps Resolution Time-to-Digital Converter Implementation Using Routing Path Delays

“…A time-to-digital converter (TDC) converts an input, which is a time interval between a start and a stop event, to a digital number [1][2][3][4]. TDCs can be realized in an analog or a digital form.…”