Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip

Rijpkema, Edwin; Goossens, Kees; Rădulescu, A.; Dielissen, J.; Meerbergen, J. van; Wielage, Paul; Waterlander, E.

doi:10.1109/date.2003.1253633

Cited by 196 publications

(89 citation statements)

References 11 publications

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“…In the presence of available bandwidth whole the bandwidth can be assigned to the lowest priority (like AEthereal). (8) But a situation of having no available best-effort traffic will lead to bandwidth underutilization for the flexible higher prioritized transactions.…”

Section: Our Bounded Arbitration Algorithm (Baa)mentioning

confidence: 99%

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QoS-supported On-chip Communication for Multi-processors

Faruque¹,

Henkel²

2007

Int J Parallel Prog

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We present a Quality of Service (QoS)-supported on-chip communication that increases the shared communication resources for multi-processor systems on chip. Time-critical embedded systems require tight guaranteed services in terms of throughput, latency etc. in order to comply to hard real-time constraints. Typically, guaranteed-service schemes require dedicated/reserved resources (i.e. links) for communication and thus suffer from low resource utilization. So improving the bandwidth utilization by using the unused bandwidth among the other competing transactions in a fair fashion is an important issue. To the best of our knowledge, we are presenting the first approach for on-chip communication that provides a high resource utilization under a transaction-specific, flexible communication scheme. It provides tight timerelated guarantees through our bounded arbitration scheme considering the lower and the upper bounds for each type of transactions. We demonstrate its advantages by means of a complete MPEG4 video decoder case study analysis and achieve under certain constraints a bandwidth utilization of up to 100% and 97% on average with a guaranteed 100% bandwidth. Thus, we provide an on-chip communication scheme that provides high bandwidth utilization while providing tight guarantee.

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Section: Our Bounded Arbitration Algorithm (Baa)mentioning

confidence: 99%

“…In the scope of this paper, support for guaranteed bandwidth, low latency, jitter and a scalable frame work for the service class assignment are specified. Previous work like (8) has summarized the service classes in: Best Effort and Guaranteed Throughput. Work in Ref.…”

Section: Application-specific Fine-grained Qos Specificationmentioning

confidence: 99%

QoS-supported On-chip Communication for Multi-processors

Faruque¹,

Henkel²

2007

Int J Parallel Prog

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“…However, no information of router implementation is presented. Aethereal offers guaranteed throughput with time division multiplexing [31]. Buffering overhead is minimized with special in-house developed FIFOs, virtual output queuing, and wormhole routing.…”

Section: Related Workmentioning

confidence: 99%

HIBI Communication Network for System-on-Chip

Salminen

Kangas

Hämäläinen

et al. 2006

J VLSI Sign Process Syst Sign Image Video Technol

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This paper presents a communication network targeted for complex system-on-chip (SoC) and network-on-chip (NoC) designs. The Heterogeneous IP Block Interconnection (HIBI) aims at maximum efficiency and minimum energy per transmitted bit combined with quality-of-service (QoS) in transfers. Other features include support for hierarchical topologies with several clock domains, flexible scalability, and runtime reconfiguration of network parameters. HIBI is intended for integrating coarse-grain components such as intellectual property (IP) blocks that have size of thousands of gates. HIBI has been implemented in VHDL and SystemC and synthesized on several CMOS technologies and on FPGA. A 32-bit wrapper requires 5400 gates and runs with 315 MHz on 0.18 μm technology which shows that only minimal area overhead is paid for the advanced features. The area and frequency results are well comparable to other NoC proposals. Furthermore, data transfers are shown to approach the maximum theoretical performance for protocol efficiency. HIBI network is accompanied with a design framework with tools for optimizing the system through automated design space exploration.

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“…Philips Research Laboratories have proposed AEthereal, a pipelined, contention-free NoC [5,6], introducing Quality-of-Service with best-effort and guaranteed throughput traffic [7]. In [8] a fully synchronous, pipelined NoC called ×pipes has been described, featuring wormhole switching with static routing tables and software tools for automatic instantiation of application specific NoCs.…”

Section: Introduction and Related Workmentioning

confidence: 99%

Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications

Milojevic

Montperrus²,

Verkest

2008

J Sign Process Syst Sign Image Video Technol

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In the near future, small electronic hand-held devices will be equipped with digital cameras capable of acquiring high resolution images (HDTV) at realtime rates, resulting in video streams of dozens of megabytes per second. The real-time video decoding and especially encoding of such streams with AVC/ H.264 or SVC standards require a huge amount of computing power that, in the case of a hand-held device, has to be delivered under the constraint of low power dissipation. In this paper we present a MultiProcessor System-on-Chip dedicated for high performance, low-power video coding applications using Network-on-Chip (NoC) as communication infrastructure. Extensive experiments have established the power dissipation models of individual NoC components, i.e. network interfaces, routers and wires. Based on these This research has been carried out in the context of IMEC's multimode multimedia program which is partially sponsored by Samsung and Freescale. The authors would also like to thank models and the NoC topology, we build the power model of the complete NoC. For three different implementation scenarios of the AVC/H.264 simple profile encoder we derive the power dissipation of the NoC for image resolutions up to HDTV at rate of 30 frames per second. The results obtained show that for the same application mapping scenario (worst case), moving from CIF to HDTV resolution will result in a 35% increase of the total power dissipation. Finally, for HDTV resolution, the difference in power dissipation between the worst (21 mW) and the best case application mapping scenario is 26%.

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Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip

Cited by 196 publications

References 11 publications

QoS-supported On-chip Communication for Multi-processors

QoS-supported On-chip Communication for Multi-processors

HIBI Communication Network for System-on-Chip

Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications

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