Trade-Off Design of Analog Circuits using Goal Attainment and "Wave Front" Sequential Quadratic Programming

Müeller,; Graeb,; Schlichtmann, Ulf

doi:10.1109/date.2007.364570

Cited by 14 publications

(12 citation statements)

References 12 publications

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“…These fronts represent trade-off hypersurfaces between the different types of circuit performance [24]- [26]. For illustration's sake, Fig.…”

Section: Vin+mentioning

confidence: 99%

“…The reason is that Pareto fronts are usually generated by using evolutionary algorithms, where a population of individuals evolves towards the best performance trade-offs. Therefore, the number of points of the Pareto fronts is necessarily limited [26]. Restricting the search space to those points would lead to suboptimal solutions; therefore, better results are obtained if circuit sizing using the statistical optimization techniques discussed in section II is applied with the circuit specifications obtained in the high-level sizing.…”

Section: Vin+mentioning

confidence: 99%

See 1 more Smart Citation

Systematic Design of High-Resolution High-Frequency Cascade Continuous-Time Sigma-Delta Modulators

Tortosa¹,

Castro-López²,

Rosa³

et al. 2008

ETRI Journal

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Ramón Tortosa (email: castro@imse.cnm.es) was with CSIC-IMSE-CNM, Sevilla, Spain, and is currently with Analog Devices, Ireland.Rafael Castro-López (phone: +34955056666), email: castro@imse.cnm.es), J.M. de la Rosa (email: jrosa@imse.cnm.es), Elisenda Roca (email: eli@imse.cnm.es), Ángel Rodríguez-Vázquez (email: angel@imse.cnm.es), and F.V. Fernández (email: pacov@imse.cnm.es) are with CSIC-IMSE-CNM and University of Sevilla, Spain. I. IntroductionThe ever shrinking minimum feature size of CMOS technologies has triggered a revolution in integrated designs, from application-specific integrated circuits to entire systems on a single chip. Notwithstanding, a critical design productivity lag has been reported [1]. With a productivity growth rate of 21%, compared to a 58% complexity growth rate, design cost is increasing rapidly. Taking into account the ever demanding time-to-market pressures, this picture is clearly worrisome. For analog and/or mixed-signal design the situation is even worse for many reasons, the most significant being the lack of commercial computer-aided design tools and methodologies to efficiently support the analog design.The design methodology described in this paper tries to reduce this design gap for a class of circuits, namely, continuous-time (CT) cascade sigma-delta (ΣΔ) modulators (conceptually shown in Fig. 1), although some of the techniques and tools presented are applicable to other classes. The choice of this circuit class has been driven by the demands of new generations of high-speed wireless and wireline communication terminals, which require broadband analog-todigital converters capable of digitizing 20 MHz wideband signals with effective resolution over 12 bits and with minimum power consumption. Although most reported ΣΔ modulators have been implemented using discrete-time (DT) circuits, the increasing demand for broadband data communication systems has motivated the use of CT techniques. In addition to showing an intrinsic anti-aliasing filtering, CT ΣΔ modulators can potentially provide faster operation with lower power consumption than their DT counterparts [2], [3].

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“…These fronts represent trade-off hypersurfaces between the different types of circuit performance [24]- [26]. For illustration's sake, Fig.…”

Section: Vin+mentioning

confidence: 99%

Section: Vin+mentioning

confidence: 99%

Systematic Design of High-Resolution High-Frequency Cascade Continuous-Time Sigma-Delta Modulators

Tortosa¹,

Castro-López²,

Rosa³

et al. 2008

ETRI Journal

View full text Add to dashboard Cite

show abstract

“…Statistical [1][2][3][4][5][6][7] as well as deterministic [8][9][10] solution approaches to Pareto optimization have been presented in the recent years. Most of these approaches compute the Pareto front of the nominal behavior of a circuit.…”

Section: Introductionmentioning

confidence: 99%

Pareto optimization of analog circuits considering variability

Graeb

Mueller-Gritschneder

Schlichtmann

2008

Circuit Theory & Apps

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SUMMARYThe trade-off between competing design objectives is often decided at the beginning of the analog sizing process by assigning weights to the design objectives. Architectural design, however, requires the knowledge of all possible optimal trade-offs of a building block. Methods for Pareto optimization provide the set of all optimal trade-offs, the so-called Pareto front. The next generation of analog Pareto optimization tools additionally has to consider the manufacturing variations. This paper describes an approach to this challenging problem. First, analog Pareto optimization will be developed as a set of specific nonlinear programming problems that provide a discretization of the Pareto front of competing performance features. Second, a general problem formulation to consider manufacturing variations and operating ranges of circuit parameters in analog Pareto optimization will be presented. Third, an efficient solution approach to the resulting tolerance Pareto optimization problem will be described. It is based on a combination of nominal Pareto optimization and realistic worst-case analysis on discrete Pareto points. It provides high efficiency at acceptable loss in accuracy.

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“…The biggest drawback of these methods is that they might stuck at local minima due to the optimization algorithms applied. An improvement, reported in [8], is to try to escape from local minima thanks to the 1 This formulation is valid for minimization problems. A simple change of sign applies for maximization.…”

Section: Pareto Optimal Frontsmentioning

confidence: 99%