Trade-off between inverse lithography mask complexity and lithographic performance

Kim, Byung-Gook; Suh, Sungsoo; Kim, Byung Sung; Woo, Sang-Gyun; Cho, Han Ku; Tolani, Vikram; Dai, Grace; Irby, Dave; Wang, Kechang; Xiao, Gao; Kim, David; Baik, Ki‐Ho; Gleason, Bob

doi:10.1117/12.824299

Cited by 44 publications

(47 citation statements)

References 14 publications

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“…ILT model based SRAF has demonstrated its significantly better performance in process window (PW) over conventional OPC approaches [2,4,5] . With increased performance with SRAF insertion, the mask write time is increased accordingly.…”

Section: Local CD Aware Selective Srafmentioning

confidence: 99%

“…In prior publications [1,2] , it has been shown that the Inverse Synthesizer (IS™) produces ILT full chip mask of contact layer with comparable mask write time with conventional OPC while maintaining the significant litho gains of ILT mask.To fully integrate ILT masks into production for all layers including line and space layers such as poly layer, a number of areas were investigated to further reduce ILT mask complexity and total e-beam shot count. These areas include flexible controls of SRAF placements with respect to local feature sizes, improved Manhattan algorithm, topology based variable Manhattan segmentation, jog alignment and mask data fracture optimization.…”

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confidence: 98%

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confidence: 98%

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Affordable and process window increasing full chip ILT masks

et al. 2010

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To enable Inverse Lithography Technology (ILT) for production as one of the leading candidates for low-k 1 lithography at 32nm and below, one major task to overcome is mask manufacturability including mask data fracturing, MRC constraints, writing time, and inspection. In prior publications [1,2] , it has been shown that the Inverse Synthesizer (IS™) produces ILT full chip mask of contact layer with comparable mask write time with conventional OPC while maintaining the significant litho gains of ILT mask.To fully integrate ILT masks into production for all layers including line and space layers such as poly layer, a number of areas were investigated to further reduce ILT mask complexity and total e-beam shot count. These areas include flexible controls of SRAF placements with respect to local feature sizes, improved Manhattan algorithm, topology based variable Manhattan segmentation, jog alignment and mask data fracture optimization. The impact of these approaches on e-beam shot count and lithography performance of ILT masks is presented in the paper.

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Section: Local CD Aware Selective Srafmentioning

confidence: 99%

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Affordable and process window increasing full chip ILT masks

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“…In addition, the maximum shot size of e-beam writer is also decreasing to obtain the high current density, so that the trend of small shot size is accelerating. Figure 8 (a) shows the mask patterns of computational lithography for wafer contact pattern [11]. According to the degree of OPC, the mask patterns of Fig.…”

Section: Figure 7 Schematic Diagram On E-beam Size Errormentioning

confidence: 99%

Requirements of e-beam size and position accuracy for photomask of sub-32 nm HP device

et al. 2010

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As semiconductor features shrink in size and pitch, there are strong needs for an advanced mask writer which has better patterning quality. Among various requirements for next photomask writer, we have focused on the requirements of ebeam size and position accuracy for hp 32nm and beyond generation.At the era of DPT, EUV, and complex OPC, the photomask is required to have extreme control of critical dimension (CD). Based on simulation and experiment, we present the e-beam requirements for advanced mask writer, in view point of stability and accuracy. In detail, the control of e-beam size in mask writer should be decreased to 0.5nm because the size error of e-beam gives rise to large CD error according to the high complexity of mask pattern. Furthermore, the drift error of beam position should be smaller than 1nm to obtain the tight pattern placement error and to minimize the edge roughness of mask pattern for the era of computational lithography and EUV lithography.

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Source-mask co-optimization (SMO) using level set methods

Tolani

Peng

et al. 2009

SPIE Proceedings

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Masks computed by use of Inverse Lithography Technology (ILT) are being increasingly used in 32nm and below nodes for their significantly better litho performance outperforming model-based OPC [1,2]. This technique poses the design of photomasks as an inverse problem and then solves for the optimal photomask using rigorous mathematical approach [3,4]. One such approach is the level set based method [5] wherein a level set function φ(x,y) is made to represent the contour of the mask. The zero level set φ(x,y)=0 then represents the actual mask at a given instance. The same level-set technique has now been extended to determine the most optimized source φ(p,q) for a given target or mask. Cooptimization of both the source and mask is a natural extension of optimizing the mask alone in ILT. The same cost function, say maximizing DOF, which is used to compute the ILT mask can be used for the source optimization as well. This approach enables accurate and fast computation of the optimized source and mask for given set of patterns and also utilizes running on a distributed computing environment. In this paper, the level set based SMO approach will be first validated on simple contact array patterns and then extended to the optimization of sample 22nm logic contact design patterns, including array, SRAM and random logic. The effect of using different emphasis in defining the cost function will also be studied.

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Trade-off between inverse lithography mask complexity and lithographic performance

Cited by 44 publications

References 14 publications

Affordable and process window increasing full chip ILT masks

Affordable and process window increasing full chip ILT masks

Requirements of e-beam size and position accuracy for photomask of sub-32 nm HP device

Source-mask co-optimization (SMO) using level set methods

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