Trace Theory and the Definition of Hierarchical Components

Rem, Martin; Snepscheut, Jan L. A. van de; Udding, Jan Tijmen

doi:10.1007/978-3-642-95432-0_13

Cited by 23 publications

(10 citation statements)

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“…Rem, van de Snepsheut and Udding's [87] definition of the set of traces resulting from parallel composition is almost identical to ours, except that it is restricted to finite length strings.…”

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confidence: 90%

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Trace Algebra for Automatic Verification of Real-Time Concurrent Systems

Burch¹

1992

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confidence: 90%

“…An agent is then modeled by a prefix-closed set of traces. To better model deadlock and divergence, this model was extended to include failures and divergences [7, 8, [87]. Dill extended this model to implement an automatic verifier for speed-independent asynchronous circuits [38.…”

Section: Chapter 1 Introductionmentioning

confidence: 99%

Trace Algebra for Automatic Verification of Real-Time Concurrent Systems

Burch¹

1992

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“…In [6,16,19], trace structures are defined to formally reason about asynchronous circuits. Trace structures are an extension of state graphs by having an additional notion of failure such that a refinement relation can be introduced for correctness implementability.…”

Section: B Trace Structuresmentioning

confidence: 99%

“…Our work is mainly focussed at the signal-level, comparable to the level being explored by current Signal transition graph and State graph based methods [2,4,10,11,20,21,22]. Trace theory has been developed by Rem, van de Snepscheut, and Udding [16,19], and by Dill [6] for the analysis and verification of speed-independent circuits. In contrast to these works, our work here is focussed on automated synthesis and hierarchical optimization.…”

Section: Introductionmentioning

confidence: 99%

Hierarchical Optimization of Asynchronous Circuits

Lin¹

1995

32nd Design Automation Conference

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-Many asynchronous designs are naturally specified and implemented hierarchically as an interconnection of separate asynchronous modules that operate concurrently and communicate with each other. This paper is concerned with the problem of synthesizing such hierarchically defined systems. When the individual components are synthesized and implemented separately, it is desirable to take into account the degrees of freedom that arise from the interactions with the other components and from the specification. Specifically, we consider how one can find the set of implementations that can be "correctly substituted" for a component in the system while preserving the behavior of the total system. The notion of correct substitution is formally defined for a hierarchical network of possibly non-deterministic modules and a new solution framework based on trace theory is presented to compute and represent this complete set of correct substitutions. We show that the complete set can be captured by a single trace structure using the notion of a "maximal trace structure". We indicate how asynchronous synthesis methods may be applied to explore the solution space e.g. to generate a delay-insensitive implementation. I INTRODUCTIONThe role of asynchronous design is gaining importance due to increasing difficulties with problems like clock skew and power dissipation. In many design scenarios, the design is most naturally described and implemented hierarchically as a network of separate asynchronous modules that operate concurrently and communicate with each other. Hierarchical representations are especially important when the design is compiled from a highlevel language. Also, implementation constraints may force their physical implementations to be separated. Indeed, real-life designs show that many asynchronous applications are inherently distributive and highly interactive, thus requiring methods to handle them. When optimizing each individual component separately, it is desirable to take into account the degrees of freedom that arise from the interactions with the other components and from the specification. This is analogous to the problem of optimizing hierarchically combinational and synchronous circuits, which has been studied extensively.For the design of asynchronous control circuits, the existing literature describes a number of automated algorithmic approaches based on Petri net and state machine models [2,4,10,11,15,20,21,22,23]. These works have focussed mainly on the synthesis and optimization of individual asynchronous modules without considering the optimization freedom available in optimizing concurrent behavior. Methods based on models of communicating processes have also been extensively studied in the literature [1,3,13,18]. These methods are mainly based on syntax-directed translation techniques. Though these methods can effectively model concurrent behavior, they also have This research was sponsored in part by the European Commission under the ESPRIT (6143) project "EXACT" and HCM contract ERBCHBG...

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“…The model is a variant of the trace theory of Rem, Snepscheut, Udding, and others[31,32,64,69,70,73,74].An execution of a circuit over time is represented as a sequence of events, called a trace. The events are transitions, which axe changes of voltage levels from logical 1 to logical 0 or vice-versa.…”

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confidence: 99%

Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits

Dill¹

1989

364

175

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A theory of automatic hierarchical verification of speed-independent circuits is developed and implemented. The theory models circuits as trace structures. Trace structures represent the behaviors of circuits as sets of traces, which are sequences of transitions on the circuit's input and output wires. Trace structures form a compositional semantics for circuits: two trace structures can be composed to model connecting the corresponding circuits and transitions can be hidden to model unobservable internal wires. Trace structures express requirements on the behavior of the environment in addition to describing the behavior of a circuit. It is noted that, for composition to work properly, a trace structure must model all possible actions of the environment. This property, called receptiveness, is precisely characterized. Trace structures can also be used as specifications. If one trace structure can be safely substituted for another in all contexts, the first is an implementation of the second. This relationship can be tested by using a decision procedure based on finding the most demanding environment with which a trace structure can be composed. The use of a single formalism for descriptions and specifications greatly simplifies the theory. More importantly, the resulting verification methodology is naturally hierarchical, because specifications at one level of abstraction can be used as descriptions at higher levels of abstraction. Two distinct theories are proposed: prefix-closed trace structures, which can model and specify safety properties, and complete trace structures, which can also deal with liveness and fairness properties. The theory of prefix-closed trace structures has been implemented in an interactive program which has verified and detected bugs in published circuit designs. Complete trace structures are based on regular languages of infinite sequences. The definitions and results pertaining to complete trace structures are very similar to those for prefix-closed trace structures. It is relatively difficult to define and test receptiveness for complete trace structures. The definition of this property is presented in terms of infinite two-player games. The problem of receptiveness is proved to be decidable, by reduction to Church's solvability problem. As always, this work would not have been possible without the help of many other people. First among these is my graduate and thesis advisor, Ed Clarke. Ed adopted me after I was orphaned (so to speak) by the departure from CMU of my previous advisor. I learned what I know about conducting research primarily from him. I first looked into the verification of asynchronous circuits on Ed's suggestion, and my first published results were achieved by analyzing a circuit that he suggested as an example. He encouraged, listened, and occasionally prodded throughout the entire duration of my thesis work. The other members of my committee, Randy Bryant, Bob SprouU, and Chuck Seitz, were unusually helpful, without exception. Each of them contributed knowledge o...

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Trace Theory and the Definition of Hierarchical Components

Cited by 23 publications

References 2 publications

Trace Algebra for Automatic Verification of Real-Time Concurrent Systems

Trace Algebra for Automatic Verification of Real-Time Concurrent Systems

Hierarchical Optimization of Asynchronous Circuits

Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits

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