Trace theory

Mazurkiewicz, Antoni

doi:10.1007/3-540-17906-2_30

Cited by 199 publications

(113 citation statements)

References 26 publications

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“…Testing that an execution satisfies a global property φ reduces therefore to verifying that every sequential execution compatible with the partial order satisfies φ or, in other terms, model checking φ on the corresponding trace. Therefore, we will see that our traces can not be seen as Mazurkiewicz traces [Maz86] where the order of independent events is meaningless.…”

Section: Introductionmentioning

confidence: 93%

Monitoring Distributed Controllers: When an Efficient LTL Algorithm on Sequences Is Needed to Model-Check Traces

Genon

Massart

Meuter

2006

FM 2006: Formal Methods

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Abstract. It is well known that through code instrumentation, a distributed system's finite execution can generate a finite trace as a partially ordered set of events. We motivate the need to use LTL model-checking on sequences and not on traces as defined by Diekert and Gastin, to validate distributed control systems executions, abstracted by such traces, and present an efficient symbolic algorithm to do the job. It uses the standard method proposed by Vardi and Wolper, which from the LTL formula, builds a monitor that accepts all the bad sequences. We show that, given a monitor and a trace, the problem to check that both the monitor and the trace have a common sequence is NP-complete in the number of concurrent processes. Our method explores the possible configurations symbolically, since it handles sets of configurations. Moreover, it uses techniques similar to the partial order reduction, to avoid exploring as many execution interleavings as possible. It works very well in practice, compared to the standard exploration method, with or without partial order reduction (which, in practice, does not work well here).

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Section: Introductionmentioning

confidence: 93%

Monitoring Distributed Controllers: When an Efficient LTL Algorithm on Sequences Is Needed to Model-Check Traces

Genon

Massart

Meuter

2006

FM 2006: Formal Methods

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“…We must also formalize the notion of dependence of operations, equivalence of runs, and equivalence robustness of properties. For detailed treatments of these notions we refer to [Ma87,Kw89,P94]. A description of the implementation of partial order reduction techniques within the Spin model checker can be found in [HP94], with a small adjustment that is explained in [HPY96].…”

Section: Visibilitymentioning

confidence: 99%

Software Model Checking

Holzmann¹,

Smith²

1999

IFIP Advances in Information and Communication Technology

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In thes notes we will review the automata-theoretic verification method and propositional linear temporal logic, with specific emphasis on their potential application to distributed software verification. An important issue in software verification is the establishment of a formal relation between the concrete, implementation-level, software application and the abstract, derived, automata-model that is the subject of the actual verification. In principle one can either attempt to derive an implementation from a verified abstract model, using refinement techniques, or one can attempt to derive a verification model from an implementation, using systematic abstraction techniques. The former method has long been advocated, but has not received much attention in industrial practice. The latter method, deriving abstract models from concrete implementations guided by explicitly stated correctness requirements, has recently begun to show considerable promise. We will discuss it in detail.

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“…We s a y that E i every nite pre x u of there exists a nite pre x w of such that u E w. T w o in nite strings and are E -related i E and E . I f E is a irre exive and symmetric relation on , then one can show that E is an equivalence relation on strings [54]. Given an irre exive and symmetric relation E, a trace is an equivalence class of nite or in nite strings induced by the equivalence relation E .…”

Section: De Nitionsmentioning

confidence: 99%

Symmetry and induction in model checking

Clarke

Jha

1995

Computer Science Today

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With the increasing complexity of digital systems, testing of digital systems is becoming increasingly important. Perhaps, the most popular method for testing hardware is simulation. The incompleteness of simulation based testing methods has spurred the recent surge in the research on formal veri cation. In formal veri cation, one builds a precise model of the hardware under scrutiny and proves that the model satis es a speci cation of interest. For example, suppose one wants to verify that a router chip does not deadlock. In this case the user will build a precise model of the router and the speci cation will express the property of deadlock freedom. The two approaches to formal veri cation are model checking and theorem proving. In this thesis we will only discuss model checking. Most model checking procedures su er from the state explosion problem, i.e., the size of the state space of the system can be exponential in the number of state variables of the system. For certain systems, exploiting the inherent symmetry can alleviate the state-explosion problem. We discuss Model Checking procedures which exploit symmetry. Current model checkers can only verify a single state-transition system at a time. We also want to extend the model checking techniques to handle in nite families of nite-state systems. In practice, nite state concurrent systems often exhibit considerable symmetry. W e i n v estigate techniques for reducing the complexity o f temporal logic model checking in the presence of symmetry. In particular, we show that symmetry can frequently be used to reduce the size of the state space that must be explored during model checking. We also investigate complexity o f v arious problems related to exploiting symmetry in model checking. Partial order based reduction techniques exploit independence of actions. We demonstrate that partial order and symmetry based reduction techniques can be applied simultaneously. The ability to reason automatically about entire families of similar state-transition systems is an important research goal. Such families arise frequently in the design of reactive systems in both hardware and software. The in nite family of token rings is a simple example. More complicated examples are trees of processes consisting of one root, several internal and leaf nodes, and hierarchical buses with di erent n umbers of processors and caches. A technique for verifying entire families of state-transition systems based on network grammars and process invariants is presented here.

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Trace theory

Cited by 199 publications

References 26 publications

Monitoring Distributed Controllers: When an Efficient LTL Algorithm on Sequences Is Needed to Model-Check Traces

Monitoring Distributed Controllers: When an Efficient LTL Algorithm on Sequences Is Needed to Model-Check Traces

Software Model Checking

Symmetry and induction in model checking

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