Trace processors: moving to fourth-generation microarchitectures

Abstract

Fundamentally new generations of microarchitectures have been occurring approximately every two decades since the 1940s. Each generation has been driven by advances in underlying hardware technologies, and by attempts to extract and realize higher degrees of instructionlevel parallelism. Given this pattern and the continued push for higher performance, we are midway through the third generation and are currently laying the groundwork for the fourth.Technology trends are clear. By the end of the next decade a single IC chip will contain several hundred million, if not a billion, transistors. The Semiconductor Industry Association's road map 1 projects processors with 350 million transistors in 2007 and with 800 million by 2010. These large numbers of transistors result from greatly reduced feature sizes and lead to higher wiring densities. Thus, a major challenge is to use these transistors effectively and to accommodate the dramatic shifts in design constraints that will result from these changes.As the sidebar "Why Large Uniprocessors?" describes, there are primarily three ways to respond to this challenge: build a multiprocessor on chip, integrate more of the computer system on a chip, or build a large uniprocessor, which would realize the fourth generation of microarchitectures. We have chosen to explore building large uniprocessors, specifically trace processors. A trace processor can execute ordinary serial programs written in standard languages at much higher speeds than are currently possible. It replicates superscalar pipelines (characteristic of the current microarchitecture generation) to form a set of connected processing elements. To this is added a level of hierarchy for control and data. A high-level control unit partitions the instruction stream into segments, or traces. A specially organized cache holds traces, and the processor fetches and executes traces as a unit. Another important feature is the heavy use of prediction for both control and data, which increases the exploitable parallelism in ordinary programs.Although we describe features of the trace processor's architecture, our goal in this article is to focus on trace processors as a vehicle for describing the requirements of a fourth-generation microarchitecture. In this we include the technology trends that drive those requirements and the underlying features to support the microarchitecture. Figure 1 diagrams the four generations of microarchitectures. The first generation (top), serial processors, began in the 1940s with the first electronic digital computers and ended in the early 1960s. Serial processors fetch and execute each instruction before going to the next. The second generation was distinguished by pipelining and similar methods for overlapping instruction execution. IBM Stretch was a precursor of this generation, and the CDC 6600 was probably the first to achieve commercial success. The 6600 was followed shortly by pipelined processors in IBM mainframes. Second-generation microarchitectures using pipelining were the norm fo...

In search of speculative thread-level parallelism

“…The Trace processor is a concrete machine proposal that can exploit similar parallelism found in multiple flows of controI [16].…”

Multiplex

“…There are several projects exploring architectural proposals for implicit threading such as Wisconsin Multiscalar [27,12] and Trace Processor [26], Stanford Hydra [15], CMU Stampede [28], Minnesota Superthreaded processor [31], Illinois Speculative NUMA [8], Speculative Multithreaded architecture [19], and SUN Microsystems MAJC [30]. While Multiplex proposes techniques to unify implicit and explicit threading within a single application, these projects have focused on employing implicit and explicit threading separately on a per application basis but not combined within one application.…”

“…Recent proposals for CMPs advocate speculative, or implicit, threading in which the hardware employs prediction to peel off instruction sequences (i.e., implicit threads) from the sequential execution stream and speculatively executes them in parallel on multiple cores [27,26,15,28,31,8,30]. Many of the proposals extend a conventional multiprocessor with the ability to handle implicit threads.…”

Impact of heterogeneity on DSM performance

“…At a fundamental level, proposed billion-transistor chip designs differ in how resources are allocated to exploit parallelism. Devoting circuit area to complex structures capable of enhancing the performance of a single thread of code [26,19,31, 81 is appealing from a software perspective, since higher performance is obtained from unmodified sequential binaries. However, uniprocessor architectures that aggressively --exploit instruction-level parallelism (ILP) require increasingly area-expensive structures.…”