Trace line failure analysis and characterization of the panel base package (PBP&amp;#x2122;) technology with fan-out capability

Yew, Ming-Chih; Wu, Chia‐Lin; Huang, Ching-Shun; Tsai, Mars; Hu, Dyi-Chung; Yang, Wen-Kung; Chiang, Kuo‐Ning

doi:10.1109/itherm.2008.4544356

Cited by 8 publications

(3 citation statements)

References 17 publications

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“…In order to reduce calculation time and increase the research efficiency, the global-local modeling approaches now are widely used, such as specific boundary constraints (SBC) method [4][5] and multi-point constraints (MPC) method [6][7][8]. Therefore, in this research MPC method is used to simulate and direct-field coupling thermal-structural FE analysis were conducted to analyze the temperature distribution of IGBT and the mechanical behaviors of bonding wire under cyclic power cycling test.…”

Section: Introductionmentioning

confidence: 99%

Thermal analysis and reliability assessment of power module under power cycling test using global- local finite element method

Chiang

Hsu

et al. 2014

2014 9th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)

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Insulated gate bipolar transistor (IGBT) power modules have acquired fast switching and low conduction loss characteristics. Because of these electrical characteristics, the IGBT has been widely applied in power supplies, e.g. hybrid electric vehicle, wind power generation, etc. However, the IGBT during rapid transient operation under high power can cause the IGBT chip to lead high junction temperature and high temperature gradients. Furthermore, because of the coefficient of thermal expansion (CTE) mismatch between the various material layers, the bonding wires and the solder joints are subjected to thermo-mechanical stress which cause solder fatigue and bonding wire failure, and then affect the reliability of IGBT under actual operation conditions. A 3-D finite element (FE) model was established base on real test samples. The simulation results found that the maximum junction temperature 112.5 is observed at the middle of IGBT chip under the load current of 40 A. Then analyze the mechanical behaviors of IGBT, the structural simulation results show that under a cyclic power environment, the stress concentration within the wire, caused by the CTE mismatch between the wire and the IGBT chip. Therefore, the wire/chip interface is the weaker portion of the power module. Finally, according to the life prediction models of literatures, this paper assessed the reliability of bonding wire in order to investigate the effects of thermal stress and strain on reliability during power cycling test.

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Section: Introductionmentioning

confidence: 99%

Thermal analysis and reliability assessment of power module under power cycling test using global- local finite element method

Chiang

Hsu

et al. 2014

2014 9th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)

Self Cite

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“…FE analysis identified metal line failure as the major reliability concern. However, a suitable trace layout design could enhance the reliability of PBP [9]. The high performance and design complexity required by the market prompted the development of eWLB.…”

Section: Introductionmentioning

confidence: 99%

Development of double-sided with double-chip stacking structure using panel level embedded wafer level packaging

Lin

Kuo

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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In recent years, consumer electronics demand has been geared towards lightweight, high capacity, and high efficiency small form factor devices. These characteristics can be achieved by using three-dimensional (3D) integrated circuit (IC) technology. This study proposes a double-chip stacking structure in an embedded fan-out wafer level packaging (WLP) with double-sided interconnections. This structure consists of two or more thin dies, chip carriers, through mold vias (TMV), and interconnection structures. The thermal performance of the proposed packaging structure is examined and discussed by using finite element (FE) analysis. An FE model of the WLP is also established to compare the thermal performance of conventional WLP and the proposed packaging structure. The proposed packaging structure has a larger size and silicon carrier, which reduces its thermal resistance from 49 °C/W to 39 °C/W. By adopting the proposed design guidelines, including carrier material selection, and designating thermal vias and chip/package size ratios, FE analysis determined that the thermal performance of the proposed packaging structure can be further improved, thereby enhancing its suitability for applications with high power density.

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“…1, the polymer is an exceptional stress buffer layer reducing the maximum shear strain in the novel fan-out WLCSP. Yew et al [6] have indicated that the redistribution traces in the fan-out WLCSP may suffer significant stress/strain, making it crack under thermal loading due to the CTE mismatch between the chip and the filler polymer. Shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

Reliability Analysis of copper interconnections of system-in-packaging structure using finite element method

Chiang

Yang

Chou

et al. 2008

2008 International Conference on Electronic Packaging Technology &Amp; High Density Packaging

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The system-in-package (SiP) is among the popular designs which meet the trend of integrated circuit (IC) development. The SiP structure investigated in this study includes seven sub-chips attached to the chip carrier, and polymer was applied around the chips. The polymer is an exceptional stress buffer layer reducing the maximum shear stress in the solder joints, but it also affects the copper interconnection which suffers from significant stress/strain concentration under thermal loading due to coefficient of thermal expansion (CTE) mismatch. In this paper, several parameter studies for a radio frequency front end module (RF-REM) incorporated with the novel wafer level chip scale package (WLCSP) technology is proposed to reduce the stress concentration behavior both in the package-level structure and the board-level structure in order to enhance reliability. In investigating the physical phenomenon of SiP structure, 2D and 3D finite element analysis (FEA) were both used. The analysis indicated that the stress concentration behavior was aggravated, especially in the vias at the chip edge. Finally, the compromised optimal location of the vias and the thickness of the adhesive are determined to minimize the stress concentration, which is due to the expansion of the filler polymer.

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Trace line failure analysis and characterization of the panel base package (PBP™) technology with fan-out capability

Cited by 8 publications

References 17 publications

Thermal analysis and reliability assessment of power module under power cycling test using global- local finite element method

Thermal analysis and reliability assessment of power module under power cycling test using global- local finite element method

Development of double-sided with double-chip stacking structure using panel level embedded wafer level packaging

Reliability Analysis of copper interconnections of system-in-packaging structure using finite element method

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