Reliability Analysis of copper interconnections of system-in-packaging structure using finite element method

Abstract

The system-in-package (SiP) is among the popular designs which meet the trend of integrated circuit (IC) development. The SiP structure investigated in this study includes seven sub-chips attached to the chip carrier, and polymer was applied around the chips. The polymer is an exceptional stress buffer layer reducing the maximum shear stress in the solder joints, but it also affects the copper interconnection which suffers from significant stress/strain concentration under thermal loading due to coefficient of thermal expansion (CTE) mismatch. In this paper, several parameter studies for a radio frequency front end module (RF-REM) incorporated with the novel wafer level chip scale package (WLCSP) technology is proposed to reduce the stress concentration behavior both in the package-level structure and the board-level structure in order to enhance reliability. In investigating the physical phenomenon of SiP structure, 2D and 3D finite element analysis (FEA) were both used. The analysis indicated that the stress concentration behavior was aggravated, especially in the vias at the chip edge. Finally, the compromised optimal location of the vias and the thickness of the adhesive are determined to minimize the stress concentration, which is due to the expansion of the filler polymer.