Towards structured ASICs using polarity-tunable Si nanowire transistors

Abstract

In addition to scaling semiconductor devices down to their physical limit, novel devices show enhanced functionality compared to conventional CMOS. At advanced technology nodes, many devices exhibit ambipolar behavior, i.e., they show n-and p-type characteristics simultaneously. This phenomenon can be tamed using double-gate structures. In this paper, we present a complete framework relying on Double-Gate-all-around Vertically stacked NanoWire FETs (DG-NWFETs). Such device enables a compact realization of arithmetic logic functions and presents unprecedented interest for structured ASIC applications.

Generating Predictive Models for Emerging Semiconductor Devices

“…The change of conduction mode is enabled by electrostatic doping of the Schottky junctions, modulating the barrier height. Programmable polarity on transistor level enables new circuit topologies as shown with a reduced transistor count XOR-gate for RFETs in general [5], [11] and the planar RFET in particular [6]. Further device level reconfiguration has been shown to reduce transistor count in VLSI circuits with area savings up to 41% [12].…”

“…For every sample n ∈ N the difference in channel current I ch is determined according to Eqn. (5). To quantify the presence of transient error, the root mean squared error (RMSE) of the current difference I ch is used as a figure of merit.…”

“…Picking up algorithm and underlying mechanisms from [3], the mathematical reasoning behind important numeric parameters and their influence on the quality of the obtained table model is addressed in Section IV. The performance of the generated RFET table model is then evaluated by conducting circuit level simulations, utilizing the reconfigurability of the RFET for compact logic cells [5], [6]. Method performance is evaluated against the TCAD model as a reference on one side and against a 13-point grid DC ramp table model, the conventional approach with comparable granularity, on the other side.…”

Nanometer-Scale Ge-Based Adaptable Transistors Providing Programmable Negative Differential Resistance Enabling Multivalued Logic

“…7,8 Moreover, it has been shown that exclusive OR (XOR)-based gates can be efficiently realized with RFETs, 9 allowing for majority-based arithmetic operations 10 that have been hindered so far in CMOS. 11,12 Another concept that has been broadly discussed to overcome the power density limits and increasing signal propagation delays of modern ultrascaled chip architectures is multivalued logic (MVL), replacing conventional binary systems by operation schemes with radices or bases higher than two. 13 Hence, the implementation of an operation scheme with higher performance employing fewer devices and interconnects compared to standard CMOS circuits, owing to higher functionality of MVL circuits, can be envisaged.…”

“…Benchmarks have shown that the use of runtime reconfiguration vs conventional CMOS can deliver compact circuit topologies, e . g ., in multibit adders and arithmetic logic units having a substantial reduction in transistor count, a smaller area footprint, and reduced latency of critical paths. , Moreover, it has been shown that exclusive OR (XOR)-based gates can be efficiently realized with RFETs, allowing for majority-based arithmetic operations that have been hindered so far in CMOS. , …”