Towards spiking neuromorphic system-on-a-chip with bio-plausible synapses using emerging devices

Saxena, Vishal; Wu, Xinyu; Srivastava, Ira; Zhu, Kehan

doi:10.1145/3109453.3123961

Cited by 10 publications

(17 citation statements)

References 32 publications

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“…Furthermore, these elements can be combined to realize analog computing parallelism, enshrined under memcomputing [3], [17], [18]. This analog computing ability is also harnessed in neuromorphic computing, where memristors realize analog synapses that learn based on spiketiming dependent plasticity (STDP), a local computing rule that is being investigated as an unsupervised learning approach for deep learning [6], [8], [10], [19]- [21].…”

Section: Memristor Characteristicsmentioning

confidence: 99%

“…Device characteristics such as the switching threshold voltages and resistances are variable (and stochastic) for each device and across several devices, and depend upon the initial 'forming' step [22]- [24]. Further, it is challenging to realize stable weights for more than 1-bit resolution in filamentary devices due to the relaxation of the filament and is currently being addressed in device research [10], [25]. HfOx and TaOx based devices have exhibited up to 9 states and their performance within a circuit is being investigated [26].…”

Section: Cmos Memristor Emulator Circuitmentioning

confidence: 99%

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A Compact CMOS Memristor Emulator Circuit and its Applications

Saxena

2018

2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)

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Conceptual memristors have recently gathered wider interest due to their diverse application in non-von Neumann computing, machine learning, neuromorphic computing, and chaotic circuits. We introduce a compact CMOS circuit that emulates idealized memristor characteristics and can bridge the gap between concepts to chip-scale realization by transcending device challenges. The CMOS memristor circuit embodies a twoterminal variable resistor whose resistance is controlled by the voltage applied across its terminals. The memristor 'state' is held in a capacitor that controls the resistor value. This work presents the design and simulation of the memristor emulation circuit, and applies it to a memcomputing application of maze solving using analog parallelism. Furthermore, the memristor emulator circuit can be designed and fabricated using standard commercial CMOS technologies and opens doors to interesting applications in neuromorphic and machine learning circuits.

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Section: Memristor Characteristicsmentioning

confidence: 99%

Section: Cmos Memristor Emulator Circuitmentioning

confidence: 99%

A Compact CMOS Memristor Emulator Circuit and its Applications

Saxena

2018

2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)

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“…We assume that an equivalent SNN is constructed through transfer learning [20], or spike-based equivalent of backpropagation algorithm [21]; the circuit architecture is essentially the same. With an estimation based on the RRAM-compatible spiking neuron chip realized in [22], 4-bit compound memristive synapses [14], [15], [23], and R LRS ranging from 0.1-10M Ω, the energy consumption for processing (training or classification) of one image is shown in Table I. By comparing with the contemporary advanced GPU Nvidia P4 [24] (170 images/s/W), a memristive architecture with R LRS = 100kΩ provides a meagre 14× improvement in energy-efficiency.…”

Section: Energy-efficiency Of Neuromorphic Socsmentioning

confidence: 99%

Energy-Efficient CMOS Memristive Synapses for Mixed-Signal Neuromorphic System-on-a-Chip

Saxena

Zhu

2018

2018 IEEE International Symposium on Circuits and Systems (ISCAS)

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Emerging non-volatile memory (NVM), or memristive, devices promise energy-efficient realization of deep learning, when efficiently integrated with mixed-signal integrated circuits on a CMOS substrate. Even though several algorithmic challenges need to be addressed to turn the vision of memristive Neuromorphic Systems-on-a-Chip (NeuSoCs) into reality, issues at the device and circuit interface need immediate attention from the community. In this work, we perform energy-estimation of a NeuSoC system and predict the desirable circuit and device parameters for energy-efficiency optimization. Also, CMOS synapse circuits based on the concept of CMOS memristor emulator are presented as a system prototyping methodology, while practical memristor devices are being developed and integrated with general-purpose CMOS. The proposed mixedsignal memristive synapse can be designed and fabricated using standard CMOS technologies and open doors to interesting applications in cognitive computing circuits.

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“…CMOS neurons and RRAM synapses are organized in a crossbar network to realize a single-level of neural interconnections as shown in Figure 1 [22,32]. In this architecture, each input neuron is connected to another output neuron through a two-terminal RRAM to form a crossbar, or cross-point array.…”

Section: Crossbar Networkmentioning

confidence: 99%

“…We assume that an equivalent SNN is constructed through transfer learning [42], or spike-based equivalent of backpropagation algorithm [46]; the circuit architecture is essentially the same. With an estimation based on the RRAM-compatible spiking neuron chip realized in [38], 4-bit compound memristive synapses [32,52,54], and R LRS ranging from 0.1-10MΩ, the energy consumption for processing (training or classification) of one image is shown in Table 1. By comparing with the contemporary GPU Nvidia P4 [55] (170 images/s/W), a memristive architecture with R LRS = 100kΩ provides a meager 14× improvement in energy-efficiency.…”

Section: Energy-efficiency Of Neuromorphic Socsmentioning

confidence: 99%

Towards Neuromorphic Learning Machines using Emerging Memory Devices with Brain-like Energy Efficiency

Saxena¹,

Wu²,

Srivastava³

et al. 2018

Preprint

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The ongoing revolution in Deep Learning is redefining the nature of computing that is driven by the increasing amount of pattern classification and cognitive tasks. Specialized digital hardware for deep learning still holds its predominance due to the flexibility offered by the software implementation and maturity of algorithms. However, it is being increasingly desired that cognitive computing occurs at the edge, i.e. on hand-held devices that are energy constrained, which is a energy prohibitive when employing digital von Neumann architectures. Recent explorations in digital neuromorphic hardware have shown promise, but offer low neurosynaptic density needed for scaling to applications such as intelligent cognitive assistants (ICA). Large-scale integration of CMOS mixed-signal integrated circuits and nanoscale emerging memory devices can enable a new generation of Neuromorphic computers that can alleviate the von Neumann bottleneck for cognitive computing tasks. Such hybrid Neuromorphic System-on-a-chip (NeuSoC) architectures promise machine learning capability at chip-scale form factors, and several orders of magnitude reduction in energy consumption. Practical demonstration of such architectures has been impeded as the performance of these emerging devices falls short of the expected behavior from the idealized analog synapses, or weights, and new learning algorithms are needed to take advantage of the device behavior. In this work, we discuss the challenges involved and present a pathway to realize ultra-lo-power mixed-signal NeuSoC, from device arrays and circuits to spike-based deep learning algorithms, with ‘brain-like’ energy-efficiency.

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Towards spiking neuromorphic system-on-a-chip with bio-plausible synapses using emerging devices

Cited by 10 publications

References 32 publications

A Compact CMOS Memristor Emulator Circuit and its Applications

A Compact CMOS Memristor Emulator Circuit and its Applications

Energy-Efficient CMOS Memristive Synapses for Mixed-Signal Neuromorphic System-on-a-Chip

Towards Neuromorphic Learning Machines using Emerging Memory Devices with Brain-like Energy Efficiency

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