A Compact CMOS Memristor Emulator Circuit and its Applications

Saxena, Vishal

doi:10.1109/mwscas.2018.8624008

Cited by 23 publications

(14 citation statements)

References 29 publications

(38 reference statements)

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“…Memristor emulators can be divided into two types according to their structures: floating memristors [3][4][5][6][7][8][9][10][11][12][13] and grounded memristors [14][15][16][17][18][19][20][21][22][23][24], with only certain memristor emulator circuits being suitable for high frequencies in the order of megahertz (MHz) [4,5,7,10,16,17,23,24]. Some of them can operate with a variable configuration, as one of the solutions proposed here, meaning that it is possible to emulate grounded or floating type of memristor with the same circuits [25][26][27].…”

Section: Introductionmentioning

confidence: 99%

Tunable flux‐controlled floating memristor emulator circuits

Petrovič

2019

IET Circuits, Devices & Systems

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This study proposes two new emulator circuits of floating (grounded) flux-controlled incremental/decremental memristor, based on modified z-copy current-voltage differencing transconductance amplifier (VDTA). The circuits use only one VDTA as an active element, a single grounded capacitor and a variable number of grounded resistors, which benefit from the integrated circuit. Furthermore, it can utilise metal-oxide-semiconductor (MOS) capacitance instead of the external capacitor in the circuit. It does not consist of any multiplication circuit block to obtain non-linear behaviour of the memristor. The parameters of the proposed memristor emulator can be tuned electronically by changing the biasing current of the VDTA. Change of the transconductance gain of the VDTA provides an advantage in the form of the externally controllable memristor. Through the simulation program with integrated circuit emphasis (SPICE) simulation which was carried out on the basis of 0.18 μm complementary MOS technology and experimental results using two MAX435 commercial devices as an active element, all theoretical assumptions and conclusions were reached in different operating frequencies, the capacitance value and process corner. The simulation test results have shown that the maximum frequency is 50 MHz.

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Section: Introductionmentioning

confidence: 99%

Tunable flux‐controlled floating memristor emulator circuits

Petrovič

2019

IET Circuits, Devices & Systems

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“…The author also introduced a first compact CMOS memristor emulator circuit [47,48] and the resulting dynamic synapse circuits [24] but concluded that non-volatile synapses are needed for long-term retention of weights, high synaptic density and low leakage power in trained neural networks. Consequently, the Neuromorphic computing architecture development requires synergistic development in devices, circuits and learning algorithms to take advantage of the high synaptic density while not being oblivious to the challenges at the device-circuit interface.…”

Section: Nanoscale Emerging Devicesmentioning

confidence: 99%

“…Furthermore, we recently showed, using a simple CMOS emulator circuit, that the pinched hysteresis characteristics of a conceptual memristor doesn't guarantee analog state retention [24,48]. Based on this discussion, we can assume the worst case scenario that many such RRAM devices in crossbar arrays, with or without setting compliance current, may end up as bistable nonvolatile memory cells.…”

Section: Challenges With Emerging Devices As Synapsesmentioning

confidence: 99%

Towards Neuromorphic Learning Machines Using Emerging Memory Devices with Brain-Like Energy Efficiency

Saxena

Srivastava³

et al. 2018

JLPEA

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The ongoing revolution in Deep Learning is redefining the nature of computing that is driven by the increasing amount of pattern classification and cognitive tasks. Specialized digital hardware for deep learning still holds its predominance due to the flexibility offered by the software implementation and maturity of algorithms. However, it is being increasingly desired that cognitive computing occurs at the edge, i.e., on hand-held devices that are energy constrained, which is energy prohibitive when employing digital von Neumann architectures. Recent explorations in digital neuromorphic hardware have shown promise, but offer low neurosynaptic density needed for scaling to applications such as intelligent cognitive assistants (ICA). Large-scale integration of nanoscale emerging memory devices with Complementary Metal Oxide Semiconductor (CMOS) mixed-signal integrated circuits can herald a new generation of Neuromorphic computers that will transcend the von Neumann bottleneck for cognitive computing tasks. Such hybrid Neuromorphic System-on-a-chip (NeuSoC) architectures promise machine learning capability at chip-scale form factor, and several orders of magnitude improvement in energy efficiency. Practical demonstration of such architectures has been limited as performance of emerging memory devices falls short of the expected behavior from the idealized memristor-based analog synapses, or weights, and novel machine learning algorithms are needed to take advantage of the device behavior. In this article, we review the challenges involved and present a pathway to realize large-scale mixed-signal NeuSoCs, from device arrays and circuits to spike-based deep learning algorithms with ‘brain-like’ energy-efficiency.

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“…The author also introduced a first compact CMOS memristor emulator circuit [26,27] and the resulting dynamic synapse circuits [28] but concluded that non-volatile synapses are needed for long-term retention of weights, high synaptic density, and low leakage power in trained neural networks. Consequently, the Neuromorphic computing architecture development requires synergistic development in devices, circuits and learning algorithms to take advantage of the high synaptic density while not being oblivious to the challenges at the device-circuit interface.…”

Section: Nanoscale Emerging Devicesmentioning

confidence: 99%

“…Furthermore, we we recently showed using a simple CMOS emulator circuit that the pinched hysteresis characteristics of a conceptual memristor doesn't guarantee analog retention [27,28]. Based on this discussion, we can assume the worst case scenario that many such RRAM devices in crossbar arrays, without setting compliance current, may end up as bistable nonvolatile memory cells.…”

Section: Challenges With Emerging Devices As Synapsesmentioning

confidence: 99%

Towards Neuromorphic Learning Machines using Emerging Memory Devices with Brain-like Energy Efficiency

Saxena¹,

Wang²,

Srivastava³

et al. 2018

Preprint

Self Cite

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The ongoing revolution in Deep Learning is redefining the nature of computing that is driven by the increasing amount of pattern classification and cognitive tasks. Specialized digital hardware for deep learning still holds its predominance due to the flexibility offered by the software implementation and maturity of algorithms. However, it is being increasingly desired that cognitive computing occurs at the edge, i.e. on hand-held devices that are energy constrained, which is energy prohibitive when employing digital von Neumann architectures. Recent explorations in digital neuromorphic hardware have shown promise, but offer low neurosynaptic density needed for scaling to applications such as intelligent cognitive assistants (ICA). Large-scale integration of nanoscale emerging memory devices with Complementary Metal Oxide Semiconductor (CMOS) mixed-signal integrated circuits can herald a new generation of Neuromorphic computers that will transcend the von Neumann bottleneck for cognitive computing tasks. Such hybrid Neuromorphic System-on-a-chip (NeuSoC) architectures promise machine learning capability at chip-scale form factor, and several orders of magnitude improvement in energy efficiency. Practical demonstration of such architectures has been limited as performance of emerging memory devices falls short of the expected behavior from the idealized memristor-based analog synapses, or weights, and novel machine learning algorithms are needed to take advantage of the device behavior. In this work, we review the challenges involved and present a pathway to realize ultra-low-power mixed-signal NeuSoC, from device arrays and circuits to spike-based deep learning algorithms, with ‘brain-like’ energy-efficiency.

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A Compact CMOS Memristor Emulator Circuit and its Applications

Cited by 23 publications

References 29 publications

Tunable flux‐controlled floating memristor emulator circuits

Tunable flux‐controlled floating memristor emulator circuits

Towards Neuromorphic Learning Machines Using Emerging Memory Devices with Brain-Like Energy Efficiency

Towards Neuromorphic Learning Machines using Emerging Memory Devices with Brain-like Energy Efficiency

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