Towards memristor based accelerator for sparse matrix vector multiplication

Cui, Jianwei; Qiu, Qinru

doi:10.1109/iscas.2016.7527185

Cited by 21 publications

(17 citation statements)

References 13 publications

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“…Towards the sparse matrix-vector multiplication based on memristor crossbar, Cui et.al. [3] propose an improved/generalized reordering algorithm based on Cuthill-McKee reordering to reduce the bandwidth of graph adjacency matrix, thus improving the efficiency of the crossbars. Whereas no blocks mapping scheme is studied after reordering.…”

Section: Related Workmentioning

confidence: 99%

“…it involves the whole sparse adjacency matrix, so full mapping of graphs on crossbar/hypercube is very resource-consuming. A preferable way is to divide the sparse matrix into blocks, and only the blocks containing non-zero elements are mapped, as mentioned in [2], [3]. However, the non-zero elements of the sparse matrix with graph structure are generally scattered, which will increase the complexity of peripheral circuits and communication between sub-crossbars (blocks), as mentioned in [3].…”

Section: Preliminarymentioning

confidence: 99%

“…In recent years, some PIM-based literature [1], [3], [4] has made effective attempts in the efficient computation of sparse graphs on the neuromorphic computing platforms. Following clustering or reordering [5] of the sparse adjacency matrix, some fixed-size partitions or progressive block partition scheme [1], [2], [4] are proposed, among which only the blocks with non-zero entries need to be stored or mapped to participate in the computation.…”

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confidence: 99%

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AutoGMap: Learning to Map Large-scale Sparse Graphs on Memristive Crossbars

Lyu¹,

Wang²,

Wen³

et al. 2021

Preprint

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The sparse representation of graphs has shown its great potential for accelerating the computation of the graph applications (e.g. Social Networks, Knowledge Graphs) on traditional computing architectures (CPU, GPU, or TPU). But the exploration of the large-scale sparse graph computing on processing-in-memory (PIM) platforms (typically with memristive crossbars) is still in its infancy. As we look to implement the computation or storage of large-scale or batch graphs on memristive crossbars, a natural assumption would be that we need a large-scale crossbar, but with low utilization. Some recent works have questioned this assumption to avoid the waste of the storage and computational resource by "block partition", which is fixed-size, progressively scheduled, or coarse-grained, thus is not effectively sparsity-aware in our view. This work proposes the dynamic sparsity-aware mapping scheme generating method that models the problem as a sequential decision-making problem which is solved by reinforcement learning (RL) algorithm (REINFORCE). Our generating model (LSTM, combined with our dynamic-fill mechanism) generates remarkable mapping performance on a small-scale typical graph/matrix data (43% area of the original matrix with fully mapping), and two largescale matrix data (22.5% area on qh882, and 17.1% area on qh1484). Moreover, our coding framework of the scheme is intuitive and has promising adaptability with the deployment or compilation system.

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Section: Related Workmentioning

confidence: 99%

Section: Preliminarymentioning

confidence: 99%

mentioning

confidence: 99%

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AutoGMap: Learning to Map Large-scale Sparse Graphs on Memristive Crossbars

Lyu¹,

Wang²,

Wen³

et al. 2021

Preprint

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“…If DFF output is low, this causes a voltage drop across the memristors that needs to be adjusted to exceed the threshold leading to an increase in its resistance. During the second clock cycle, the same procedure will be applied but in the opposite manner 6 . The downside of using the inverters of DFFs in conjunction with Ziksa unit is that the network will suffer from the sneak path issue especially during the learning phase.…”

Section: Mini-column Learningmentioning

confidence: 99%

Neuromemrisitive Architecture of HTM with On-Device Learning and Neurogenesis

Zyarah

Kudithipudi

2019

J. Emerg. Technol. Comput. Syst.

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Hierarchical temporal memory (HTM) is a biomimetic sequence memory algorithm that holds promise for invariant representations of spatial and spatiotemporal inputs. This paper presents a comprehensive neuromemristive crossbar architecture for the spatial pooler (SP) and the sparse distributed representation classifier, which are fundamental to the algorithm. There are several unique features in the proposed architecture that tightly link with the HTM algorithm. A memristor that is suitable for emulating the HTM synapses is identified and a new Z-window function is proposed. The architecture exploits the concept of synthetic synapses to enable potential synapses in the HTM. The crossbar for the SP avoids dark spots caused by unutilized crossbar regions and supports rapid on-chip training within 2 clock cycles. This research also leverages plasticity mechanisms such as neurogenesis and homeostatic intrinsic plasticity to strengthen the robustness and performance of the SP. The proposed design is benchmarked for image recognition tasks using MNIST and Yale faces datasets, and is evaluated using different metrics including entropy, sparseness, and noise robustness. Detailed power analysis at different stages of the SP operations is performed to demonstrate the suitability for mobile platforms.

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“…Nonvolatile emerging memory devices such as memristors have been successfully adopted in hardware accelerators for machine learning (1)(2)(3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15). Organized into a crossbar array, these devices implement vector matrix multiplication (VMM), a computationally expensive operation within one step regardless of the array size, resulting in orders of magnitude higher computing throughput (16,17).…”

Section: Introductionmentioning

confidence: 99%