Towards low-loss monolithic silicon and nitride photonic building blocks in state-of-the-art 300mm CMOS foundry

Abstract

We review recent progress in loss reduction of Si and SiN waveguides in GLOBALFOUNDRIES 300mm monolithic Si photonics platform. Primary challenges to creating low-loss CMOS integrated photonic components are highlighted and potential solutions are outlined.

Wafer-level testing of inverse-designed and adjoint-inspired dual layer Si-SiN vertical grating couplers

“…In this paper, we experimentally validated two different design paradigms for perfectly vertical dual layer Si+SiN single-polarization GCs: GCs designed using inverse design based on the adjoint method (as proposed in our previous work [11]), and adjoint-inspired GCs (adapting the technique proposed in [36] to the dual layer stack). These devices were fabricated on a hybrid Si/SiN platform using scalable immersion DUV lithography on 300 mm wafers, with critical dimensions (60 nm) for the c-Si layer as well as relatively high aspect ratios (6 : 1) for the SiN features that can be considered state-of-the-art for the silicon photonics community [29][30][31][32][33][34][35]. For both design methodologies, using WLT, for the first time, we experimentally demonstrated record low median IL of 1.3 dB (with interquartile range of ∼0.1−0.2 dB) for perfectly vertical coupling for dual layer device designs that are compatible with volume fabrication, which is ∼0.5 dB better than our previously demonstrated single layer, single-etch c-Si alternative [36].…”

“…Both Si and SiN layers are patterned with an advanced DUV immersion lithography with a minimum feature size of 60 nm (100 nm) for the Si layer (SiN respectively). The patterning of the SiN, with these critical dimensions and aspect ratios developed by the foundry [29][30][31], can be considered state-of-the-art when compared with similar platforms currently developed by other foundries [32][33][34][35].…”

“…In this paper, we apply advanced design techniques to GC design in an emerging hybrid c-Si/SiN layer stack [29][30][31][32][33][34][35]. Specifically, we investigate perfectly vertical GCs as the 0 deg coupling might simplify the mechanical design of single-mode connectors in datacom or HPC interconnects [3,11].…”

Design Methodologies for Integrated Quantum Frequency Processors

“…All simulations are performed in silicon at 300 K, with a fixed waveguide cross-section of 480 nm × 220 nm (width × height), for which we precompute the spectrally dependent effective index n eff (ω) for the TE polarization using a numerical eigenmode solver. In the interest of presenting an aggressiveyet feasible and foundry-compatible system [54], [55]-we assume a nominal waveguide attenuation of 0.5 dB/cm (α = 0.115 cm −1 ), ring radii r ≈ 20 µm, and symmetric coupling constants κ 2 1 = κ 2 2 κ 2 = 0.01 for each ring in the pulse shaper, comfortably in the overcoupled regime (t 1 = t 2 < A) as desired for an efficient drop port response. Further, ω0 2π = 193 THz and ∆ω 2π = 15 GHz define the nominal frequency mode space ω m used by the pulse shaper (in the telecom band).…”