Towards high-performance p-type two-dimensional field effect transistors: contact engineering, scaling, and doping

Abstract

N-type field effect transistors (FETs) based on two-dimensional (2D) transition metal dichalcogenides (TMDs) like MoS2 and WS2 have come closer to meeting the requirements set forth in International Roadmap for Devices and Systems (IRDS). However, p-type 2D FETs are dramatically lagging behind in meeting performance standards. Here, we adopt a three-pronged approach that includes contact engineering, channel length (Lch) scaling, and monolayer doping to achieve high-performance p-type FETs based on synthetic WSe2. Using electrical measurements backed by atomistic imaging and rigorous analysis, Pd was identified as the favorable contact metal for Wse2 owing to better epitaxy, larger grain size, and higher compressive strain leading to lower Schottky barrier height. While the ON-state performance of Pd-contacted WSe2 FETs was improved by ~10× by aggressively scaling Lch from 1 µm down to ~ 20 nm, ultra-scaled FETs were found to be contact limited. To reduce the contact resistance, monolayer tungsten oxyselenide (WOxSey) obtained using self-limiting oxidation of bilayer WSe2 was used as p-type dopant. This led to ~ 5× improvement in the ON-state performance and ~ 9× reduction in the contact resistance. We were able to achieve a median ON-state current as high as ~ 10 µA/µm for ultra-scaled and doped p-type WSe2 FETs with Pd contacts. We also show the applicability of our monolayer doping strategy to other 2D materials, like MoS2, MoTe2, and MoSe2.

Room Temperature Negative Differential Resistance with High Peak Current in MoS2/WSe2 Heterostructures

“…In contrast, Cr/Au contacts on few-layer WSe 2 exhibit n-type transport while the vdW Pt contacts show p-type-dominant behavior. 19 This result is consistent with previous studies showing that vdW contacts are effective in achieving p-type transport in WSe 2 . 15,20 In addition, temperature-dependent transport measurements showing stable transport behavior over a large temperature range are shown in Figure S2.…”

Self-Aligned Top-Gate Structure in High-Performance 2D p-FETs via van der Waals Integration and Contact Spacer Doping

“…The linear change in V th as a function of V BG indicates effective gate-controllability, attributed to clean vdW TG interface, which is essential for reliable FET operation. 31 We also explored the thickness-dependent performance of our device with various WSe 2 thicknesses of 2, 3, 6, and 9 nm. Figure S6 represents the WSe 2 thickness dependent I D − V TG characterization of these devices, exhibiting a higher p-type on-current in the thinner samples.…”