Towards evolving electronic circuits for autonomous space applications

Lohn, Jason; Haith, Gary; Colombano, Silvano; Stassinopoulos, Dimitris

doi:10.1109/aero.2000.878523

Cited by 11 publications

(17 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In [10,11], Lohn and Colombano use GAs to develop a compact circuit representation that decreases the complexity of evolutionary design of analog circuitry. While their representation restricts potential topologies, it decreases runtimes significantly by maximizing the number of useful circuits in the population.…”

Section: Introductionmentioning

confidence: 99%

“…Based on previous work [8,10,11,16], it seemed unlikely that a GA could successfully fabricate the high-power amplifiers necessary for open-loop amplification and control. Additionally, work on charge recovery [12] and complementary waveform behavior [15] would be quite difficult or impossible to replicate using a GA. For these reasons, this paper focuses on closed-loop control of the piezo robot.…”

Section: The Piezo Robotmentioning

confidence: 99%

“…GAUL provides a modular GA evolution environment and allows the user to specify crossover and mutation methods, statistical selection, elitism, and other GA parameters [4]. Based on previous work, the crossover and mutation rates were set to 80% and 20% respectively [8,10,11]. Double point crossover and tournament selection were used, and parents were allowed to survive into subsequent generations.…”

Section: Genetic Algorithm Descriptionmentioning

confidence: 99%

“…Two models are developed for the robot actuators, and a GA is used to synthesize controllers for both models. A modified version of the compact circuit representation in [10,11] is used by a GA to evolve variable topology controllers with minimum population sizes and runtimes. Several fitness functions, including one similar to the one in [18], are used to determine fitness.…”

Section: Introductionmentioning

confidence: 99%

“…As such, the Government retains a nonexclusive, royalty-free right to publish or reproduce this article, or to allow others to do so, for Government purposes only. GECCO'06, July [8][9][10][11][12]2006 [8,10,11], Zebelum and Pacheco pre-specify the number of internal and external circuit nodes prior to synthesis. While successful, Zebelum's technique greatly limits the number of possible topologies during controller synthesis and, thus, excludes potentially useful controllers from entering the population.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Evolutionary design of fault-tolerant analog control for a piezoelectric pipe-crawling robot

Hollinger

Gwaltney

2006

Proceedings of the 8th Annual Conference on Genetic and Evolutionary Computation

View full text Add to dashboard Cite

In this paper, a genetic algorithm (GA) is used to design faulttolerant analog controllers for a piezoelectric micro-robot. Firstorder and second-order functions are developed to model the robot's piezoelectric actuators, and the GA is used to evolve closed-loop controllers for both models. The GA is first used to assist in traditional PID design and is later used to synthesize variable topology analog controllers. Through the use of a compact circuit representation, runtimes are minimized and controllers are synthesized with minimum population sizes and components. Fault-tolerance is built into the fitness function to facilitate the design of controllers robust to both actuator failure and component failure. The GA is successfully used to design synthetic controllers and to optimize a traditional PID design. This research shows the advantages of GA assisted design when applied to robot-control problems.

show abstract

Section: Introductionmentioning

confidence: 99%

Section: The Piezo Robotmentioning

confidence: 99%

Section: Genetic Algorithm Descriptionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Evolutionary design of fault-tolerant analog control for a piezoelectric pipe-crawling robot

Hollinger

Gwaltney

2006

Proceedings of the 8th Annual Conference on Genetic and Evolutionary Computation

View full text Add to dashboard Cite

show abstract

Evolutionary design and adaptation of high performance digital filters within an embedded reconfigurable fault tolerant hardware platform

Hounsell

Arslan

Thomson

2004

Soft Computing - A Fusion of Foundations, Methodologies and App

View full text Add to dashboard Cite

Finite impulse response filters (FIRs) are crucial devices for robust data communication and manipulation. Multiplierless filters have been shown to produce high performance systems with fast signal processing and reduced area. Furthermore, the distributed architecture inherent in multiplierless filters makes it a suitable candidate for fault tolerant design. Alternative approaches to the design of fault tolerant systems have been proposed using evolutionary algorithms (EAs) and the concept of evolvable hardware (EHW). This paper presents an evolvable hardware platform for the automated design and adaptation of multiplierless digital filters. Filters are realised within a dedicated programmable logic array (PLA) based on the Primitive Operator Filter design principle. The platform employs a genetic algorithm to autonomously configure the PLA for a given set of coefficients. The ability of the platform to adapt to increasing numbers of faults was investigated through the ''evolution'' of a 31-tap lowpass FIR filter. Results show that the functionality of filters evolved on the PLA was maintained despite an increasing number of faults covering up to 25% of the PLA area. Additionally, three PLA initialisation methods were investigated to ascertain which produced the fastest fault recovery times. It was shown that seeding a population of random configuration-strings with the best configuration currently obtained resulted in a 6 fold increase in fault recovery speed over other methods investigated.

show abstract

Grammatical Evolution of Complex Digital Circuits in SystemVerilog

2022

View full text Add to dashboard Cite

The evolution of complex circuits remains a challenge for the Evolvable Hardware field in spite much effort. There are two major issues: the amount of testing required and the low evolvability of representation structures to handle complex circuitry, at least partially due to the destructive effects of genetic operators. A 64-bit $$\times$$ × 64-bit add-shift multiplier circuit modelled at register-transfer level in SystemVerilog would require approximately 33,200 gates when synthesized using Yosys Open SYnthesis Suite tool. This enormous gate count makes evolving such a circuit at the gate-level difficult. We use Grammatical Evolution (GE) and SystemVerilog, a hardware description language (HDL), to evolve fully functional parameterized Adder, Multiplier, Selective Parity and Up–Down Counter circuits at a more abstract level other than gate level—register transfer level. Parameterized modules have the additional benefit of not requiring a re-run of evolutionary experiments if multiple instances with different input sizes are required. For example, a 64-bit $$\times$$ × 64-bit and 128-bit $$\times$$ × 128-bit multipliers etc., can be instantiated from a fully evolved functional and parameterized N-bit $$\times$$ × N-bit multiplier. The Adder (6.4$$\times$$ × ), Multiplier (10.7$$\times$$ × ) and Selective Parity (6.7$$\times$$ × ) circuits are substantially larger than the current state of the art for evolutionary approaches. We are able to scale so dramatically because of the use of a HDL, which permits us to operate at a register-transfer level. Furthermore, we adopt a well known technique for reducing testing from digital circuit design known as corner case testing. Skilled circuit designers rely on this to avoid time-consuming exhaustive testing. We demonstrate a simple way to identify and use corner cases for evolutionary testing and show that it enables the generation of massively complex circuits. All circuits were successfully evolved without resorting to the use of any standard decomposition methods, due to our ability to use programming constructs and operators available in SystemVerilog.

show abstract

Towards evolving electronic circuits for autonomous space applications

Cited by 11 publications

References 14 publications

Evolutionary design of fault-tolerant analog control for a piezoelectric pipe-crawling robot

Evolutionary design of fault-tolerant analog control for a piezoelectric pipe-crawling robot

Evolutionary design and adaptation of high performance digital filters within an embedded reconfigurable fault tolerant hardware platform

Grammatical Evolution of Complex Digital Circuits in SystemVerilog

Contact Info

Product

Resources

About