Towards Efficient Verification of Arithmetic Algorithms over Galois Fields GF(2m)

Morioka, Sumio; Katayama, Y.; Yamane, Toshiyuki

doi:10.1007/3-540-44585-4_45

Cited by 15 publications

(12 citation statements)

References 12 publications

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“…The S-Box circuit can be obtained from its truth table by using two-level logic such as SOP, POS (Product of Sums), PPRM [11], or by using decision diagrams such as BDD (Binary Decision Diagram) [15]. Our investigations' results in [16,17] show that the variable ordering of the BDD does not have much effect on the size and speed of the S-Box and GF inverter. Based on this research, we designed a very fast S-Box called twisted-BDD [17], which is 1.5 to 2 times faster than the other S-Box implementations.…”

Section: Various S-box Circuit Implementationsmentioning

confidence: 83%

“…Because P 17 is always an element of GF( (2 2 ) 2 ) (i.e., the upper 4 bits of P 17 are always 0), computing the upper 4 bits of P 17 is unnecessary [8]. The value of ( P 17 ) -1 is computed recursively over GF( (2 2 ) 2 ), then multiplied by P 16 over GF(( (2 2 ) 2 ) 2 ), and finally P -1 is obtained. This final multiplication requires fewer circuit resources than conventional multiplication over GF (2 8 ), because P 17 is an element of GF( (2 2 ) 2 ).…”

Section: A S-box Implementation Based On Composite Field Techniquementioning

confidence: 99%

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An Optimized S-Box Circuit Architecture for Low Power AES Design

Morioka

Satoh

2003

Lecture Notes in Computer Science

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163

109

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Abstract. Reducing the power consumption of AES circuits is a critical problem when the circuits are used in low power embedded systems. We found the S-Boxes consume much of the total AES circuit power and the power for an S-Box is mostly determined by the number of dynamic hazards. In this paper, we propose a low-power S-Box circuit architecture: a multi-stage PPRM architecture over composite fields. In this S-Box, (i) the signal arrival times of gates are as close as possible if the depths of the gates from the primary inputs are the same, and (ii) the hazard-transparent XOR gates are located after the other gates that may block the hazards. A low power consumption of 29 mW at 10 MHz using 0.13 mm 1.5V CMOS technology was achieved, while the consumptions of the BDD, SOP, and composite field S-Boxes are 275, 95, and 136 mW, respectively.

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Section: Various S-box Circuit Implementationsmentioning

confidence: 83%

Section: A S-box Implementation Based On Composite Field Techniquementioning

confidence: 99%

An Optimized S-Box Circuit Architecture for Low Power AES Design

Morioka

Satoh

2003

Lecture Notes in Computer Science

Self Cite

163

109

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“…The theorem-proving approach of [11] also verify a Galois Field GF (2 k ) implementation against a given specification. They devise a decision procedure based on polynomial division, variable elimination, term re-writing, etc., and demonstrate a correctness proof of a sub-block of a Reed-Solomon decoder.…”

Section: Related Previous Workmentioning

confidence: 99%

Verification of composite Galois field multipliers over GF ((2<sup>m</sup>)<sup>n</sup>) using computer algebra techniques

Kalla

Enescu

2011

2011 IEEE International High Level Design Validation and Test Workshop

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Galois field computations abound in many applications, such as in cryptography, error correction codes, signal processing, among many others. Multiplication usually lies at the core of such Galois field computations, and is one of the most complex operations. Hardware implementations of such multipliers become very expensive. Therefore, there have been efforts to reduce the design complexity by decomposing the Galois field GF(2 k ) as GF ((2 m ) n ) where k = m × n. Such a decomposition introduces a hierarchical abstraction -lifting the ground field from GF (2) (bit-level) to GF (2 m ) (word-level) -thus simplifying the design. This paper addresses the formal verification problem of such multipliers designed over GF ((2 m ) n ), using a computer algebra and algebraic geometry based approach. To prove that the composite field multiplier implementation matches the original specification, we hierarchically formulate the verification problem using the Hilbert's Nullstellensatz over Galois Fields. A Gröbner basis engine is employed as the underlying computational framework. Experiments are performed with various variable/term orders to demonstrate the efficacy of our approach. We can verify the correctness of upto 1024-bit multipliers, whereas SAT/SMT-based approaches are infeasible.

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“…Morioka et.al. proposed a logic system for the verification of algorithms over Galois fields GF (2 m ) and carried out a proof for One Shot ReedSolomon Decoding Algorithm [14]. Mukhopadhyay et.…”

Section: Introductionmentioning

confidence: 99%

Formal Verification of Hardware Support for Advanced Encryption Standard

Slobodová

2008

2008 Formal Methods in Computer-Aided Design

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The Advanced Encryption Standard (AES), approved by National Institute of Standards and Technology, specifies a cryptographic algorithm that can be used to protect electronic data. The next generation of Intel micro-processor introduces a set of instructions known as AES-NI, that promises multi-folded acceleration of the AES encryption and decryption process. In this paper, we report about the formal verification of hardware support for these new instructions. The verification is based on use of Symbolic Trajectory Evaluation that lies at the base of formal verification methodology used by Intel Corporation. To our knowledge, this is the first formal verification of AES hardware support.

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Towards Efficient Verification of Arithmetic Algorithms over Galois Fields GF(2m)

Cited by 15 publications

References 12 publications

An Optimized S-Box Circuit Architecture for Low Power AES Design

An Optimized S-Box Circuit Architecture for Low Power AES Design

Verification of composite Galois field multipliers over GF ((2<sup>m</sup>)<sup>n</sup>) using computer algebra techniques

Formal Verification of Hardware Support for Advanced Encryption Standard

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