An Optimized S-Box Circuit Architecture for Low Power AES Design

Morioka, Sumio; Satoh, Akashi

doi:10.1007/3-540-36400-5_14

Cited by 163 publications

(114 citation statements)

References 17 publications

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“…Unless the special design is made as described in Ref. [12], the input signals at the gates have the different number of logic steps and are easy to cause differences in the delay time. On the contrary, since the number of gates connected to each complementary output of WDDL is equal as described above, the difference of place-and-route is predominant over a difference in the delay time between a andā (or b andb).…”

Section: Countermeasures Against Main Factors Of Leakage In Wddlmentioning

confidence: 99%

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Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style

Suzuki

Saeki

2006

Lecture Notes in Computer Science

115

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Abstract. In recent years, some countermeasures against Differential Power Analysis (DPA) at the logic level have been proposed. At CHES 2005 conference, Popp and Mangard proposed a new countermeasure named Masked Dual-Rail Pre-Charge Logic (MDPL) which combine dual-rail circuits with random masking to improve Wave Dynamic Differential Logic (WDDL). The proposers of MDPL claim that it can implement secure circuits using a standard CMOS cell library without special constraints for the place-and-route because the difference of loading capacitance between all pairs of complementary logic gates in MDPL can be covered up by the random masking. In this paper, we especially focus the signal transition of the MDPL gate and evaluate the DPA-resistance of MDPL in detail. Our evaluation results show that the leakage occurs in the MDPL gates as well as WDDL gates when input signals have difference of delay time even if MDPL has an effectiveness on reducing the leakage caused by the difference of loading capacitance. Furthermore, we demonstrate the problem with different input signal delays by measurements of an FPGA and show the validity of our evaluation.

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Section: Countermeasures Against Main Factors Of Leakage In Wddlmentioning

confidence: 99%

“…The S-box design method for low power consumption proposed by Morioka et al is recommended as one technique to reduce inevitable leakage [12]. In the circuit design, it generally needs high effort to adjust the delay time between the input signals at each gate.…”

Section: Countermeasures Against Main Factors Of Leakage In Wddlmentioning

confidence: 99%

Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style

Suzuki

Saeki

2006

Lecture Notes in Computer Science

115

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“…field that transform GF (2 8 ) to GF ( (2 4 ) 2 ) or transform GF (2 8 ) to GF(( (2 2 ) 2 ) 2 ), as in [8]- [10]. …”

Section: International Journal Of Computer Theory and Engineering Volmentioning

confidence: 99%

A New Approach for Designing Key-Dependent S-Box Defined over GF (24) in AES

El-Sheikh¹,

El-Mohsen²,

Elgarf³

et al. 2012

IJCTE

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Abstract-In this paper a new approach for designing S-box in Advanced Encryption Standard (AES) is proposed. The proposed S-box is constructed from small S-boxes defined over GF (2 4 ) instead of GF (2 8 ) as in traditional AES. Rijndael Algorithm (RA), as one of AES standards, is modified by applying the new approach. The Modified Rijndael Algorithm (MRA) is constructed by replacing the S-box of RA by small S-boxes, and the key expansion procedure of RA is modified consequently. Each one of the small S-boxes has different equation and each equation is extracted using one of the three irreducible polynomials existing in GF (2 4 ). So, detecting different equations by cryptanalysts is very difficult compared to the S-box of RA which uses one equation and one irreducible polynomial. The substitution from small S-boxes is done based on the round key, so this achieves diffusion, confusion and therefore security for MRA. The MRA is tested using avalanche effect and strict avalanche criterion (SAC) to evaluate security. The performance evaluation is calculated and proved that MRA is more suitable for the applications that require security and QoS such as voice over IP (VoIP).Index Terms-AES, key dependent S-box, finite field, cryptographic algorithms, strict avalanche criterion. I. INTRODUCTIONThe Advanced Encryption System (AES) was launched as a symmetrical cryptography standard algorithm by the National Institute of Standard and Technology (NIST) in October 2000, after a four year effort to replace the aging DES, NIST announced the selection of Rijndael, as in [1], [2] as the proposed AES (NIST 2004). Draft of the Federal Information Processing Standard (FIPS), as in [3] for the AES was published in February 2001; Standardization of AES was approved after public review and comments, and published a final standard FIPS as in [3] in December 2001. Standardization was effective in May 2002 (NIST 2004. Rijndael submitted by Joan Daemen and Vincent Rijmen (Daemen 1998), is a symmetric key, iterated block cipher based on the arithmetic in the Galois Field of 2 8 elements -GF (2 8 ). The Rijndael proposal for AES defined a cipher in which the block length and the key length can be independently specified to be 128, 192, or 256 bits. The AES specification uses the same three key size alternatives but limits the block length to 128 bits, as in [4]. The input to the Manuscript received February 17, 2012; revised March 31, 2012. Hanem M. El-Sheikh was with the Faculty of Engineering, Alexandria University, Alexandria, Egypt (e-mail: honymora@yahoo.com).Omayma A. Mohsen is with the Switching Department, and the scientific committee at the National Telecommunication Institute.Abdelhalim Zekry is with the electronics at faculty of Engineering, Ain Shams University, Cairo, Egypt. encryption and decryption algorithms is a single 128-bit block and this block is depicted as a square matrix of bytes. The key that is provided as input is expanded into an array of key schedule words, each word is four bytes and the total key schedule ...

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“…In the folded architecture [10], four AES S-Boxes are used in the SubBytes transformation and another S-Box is used in the key scheduling process. The architecture is improved by only using four total S-Boxes in both the SubBytes transformation and the key scheduling process, which is called the modified folded AES architecture.…”

Section: Design Criteria: Power Vs Areamentioning

confidence: 99%

Compact Design of the Advanced Encryption Standard Algorithm for IEEE 802.15.4 Devices

Song¹,

Kim²

2011

Journal of Electrical Engineering and Technology

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-For low-power sensor networks, a compact design of advanced encryption standard (AES) algorithm is needed. A very small AES core for ZigBee devices that accelerates computation in AES algorithms is proposed in this paper. The proposed AES core requires only one S-Box, which plays a major role in the optimization. It consumes less power than other block-wide and folded architectures because it uses fewer logic gates. The results show that the proposed design significantly decreases power dissipation; however, the resulting increased clock cycles for 128-bit block data processing are reasonable for IEEE 802.15.4 standard throughputs.

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An Optimized S-Box Circuit Architecture for Low Power AES Design

Cited by 163 publications

References 17 publications

Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style

Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style

A New Approach for Designing Key-Dependent S-Box Defined over GF (24) in AES

Compact Design of the Advanced Encryption Standard Algorithm for IEEE 802.15.4 Devices

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