Towards Contact Resistance Minimization through CoSi₂Formation Process Optimization on P-Doped Poly-Si by Hot Wall-Based Rapid Thermal Annealing

Abstract

The effect of annealing temperature and time on the resulting resistivity of CoSi 2 contacts with P-doped poly-Si was investigated using a single wafer furnace-based (hot wall) rapid thermal annealing (RTA) system. To achieve low resistivity contacts, CoSi 2 formation process optimization was done by detailed design of experiment (DOE). Sheet resistance (Rs) response surface plots as a function of annealing temperature and time for 1 st step and 2 nd step RTA processes showed a very wide process window. The hot wall RTA resulted in significantly (>20%) lower Rs, over a very wide process window, compared to the equivalent RTA process using conventional tungsten halogen lamp-based (cold wall) RTA systems. Dopant (P) depth profiling results by secondary ion mass spectroscopy (SIMS) revealed that the P atoms in the CoSi 2 film and at the CoSi 2 /P-doped poly-Si interface, redistribute very differently under different RTA conditions. The CoSi 2 formation process was optimized utilizing characteristics of P pile-up near the CoSi 2 /P-doped poly-Si interface to suppress P depletion from the P-doped poly-Si layer for contact resistance minimization. Low resistivity junctions and low resistivity contacts are essential for fabricating high performance devices for advanced device nodes.1-6 A high contact resistance negatively affects device operation speed and generates undesired local heating. Any variations in the contact resistance among devices within a chip can significantly lower the overall chip performance and possibly device yield in production. Significant effort has been expended to develop low resistivity junctions, industry wide.7-18 However, low resistivity contact formation has not received significant attention, other than changing the silicide of choice, depending on required minimum line width or device node parameters. Silicidation process is believed to be well understood and established. Once the candidate silicide material has been chosen for the device node, relatively small improvements in resistivity have been made in recent years, despite silicidation process optimization which includes modifications of process steps and integration schemes. Tight process control and accumulation of small improvements in every process step are required in developing and volume manufacturing of advanced devices.It is well known that silicide formation on different Si phases (amorphous, polycrystalline or monocrystalline) takes place at different temperatures and at different rates. 6,8,16,18 Dopant species and concentration also play important roles in silicide formation and defect generation.9,12,13 Tungsten silicide, titanium silicide, cobalt silicide and nickel silicide formation studies on various Si phases and structures, including silicon-on-insulator (SOI) wafers, have been reported for several decades.1-18 Sometimes, ion implantation on silicide layers is done to reduce line width dependence thus potentially extending the lifecycle of the selected silicide for the next generation devices with narrower line ...

(Invited) Pattern and Emissivity Insensitive Dopant Activation and Silicide Contact Formation Annealing in a Hot Wall Rapid Thermal Annealing System

“…The process window narrowing and shift as large as 125 o C have been reported. [15][16][17] C. Localized Sheet Resistance Non-uniformity Forty nine (49)-point sheet resistance wafer mapping results on metal films on Si wafers typically show good within wafer uniformity and wafer-to-wafer repeatability of most of wafers, regardless of RTA systems used, except for phase transition temperature regions. Only 7 points are measured across the wafer.…”

“…10). [15,16] For comparison purposes, SIMS depth profiles of a Co/p-doped poly-Si/SiO 2 /Si wafer immediately after 1st step RTA, using the cold wall RTA system, and a 1st step annealed Co/p-doped poly-Si/SiO 2 /Si wafer after wet etching were also plotted.…”

Thermal Silicidation of Ni/SiGe and Characterization of Resulting Nickel Germanosilicides

“…Thermal silicidation was performed using TiN/Ni/Si 1-x Ge x /Si/SiO 2 /Si wafers with different Ge content in a stacked hotplate-based SAO-302LP system designed for 300 mm wafers. 9,[21][22][23][24] Thicknesses of the TiN, Ni, Si 1-x Ge x , Si and SiO 2 layers were 5, 9, 80, 20 and 140 nm, respectively. Physical vapor deposited (PVD or sputtered) TiN (5 nm) capped Ni films (9 nm) were used.…”

“…Details of the annealing system (SAO-302LP), wafer temperature profile and other low temperature process applications (NiSi, Cu annealing and SOG annealing) results have been reported elsewhere. 9,[21][22][23][24] Unlike other annealing systems, the SAO-302LP system does not control wafer temperature directly and annealing time is also counted differently. For easy understanding, wafer temperature profiles at hot plate temperature set points of 200 °C, 300 °C and 400 °C are plotted in Fig.…”

Effect of Substrate Type on CoSi2 Formation in Rapid Thermal Annealing

“…Development efforts on the high integrity junctions and low resistivity contacts have always been conducted in parallel (5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15)(16). Low resistivity contact formation has not received significant attention until very recently compared to that for high integrity junction formation.…”