Towards Automatic and Agile AI/ML Accelerator Design with End-to-End Synthesis

Proceedings of the 19th ACM International Conference on Computing Frontiers

Tumeo³

et al. 2022

Self Cite

Section: Approachmentioning

confidence: 99%

Hardware acceleration of complex machine learning models through modern high-level synthesis

Proceedings of the 19th ACM International Conference on Computing Frontiers

Tumeo³

et al. 2022

Self Cite

“…Figure 1 provides an overview of the SODA Synthesizer [4], [5], [6]; components extended to support the generation of dataflow architectures are highlighted in blue. The tool is composed of two main parts: a compiler-based frontend and a compiler-based hardware synthesis engine.…”

Section: The Soda Synthesizermentioning

confidence: 99%

“…To address these problems, we have developed the SOftware Defined Architectures (SODA) Synthesizer [4], [5], [6]: an open-source, multi-level, modular, extensible, nohuman-in-the-loop hardware compiler that translates highlevel ML models into domain-specific accelerators. Our tool generates highly specialized designs in a hardware description language (HDL), which can be synthesized with both commercial and open-source tools on field programmable gate arrays (FPGAs) or as application-specific integrated circuits (ASICs).…”

Section: Introductionmentioning

confidence: 99%

End-to-End Synthesis of Dynamically Controlled Machine Learning Accelerators

Castellana

et al. 2022

IEEE Trans. Comput.

Self Cite

Edge systems are required to autonomously make real-time decisions based on large quantities of input data under strict power, performance, area, and other constraints. Meeting these constraints is only possible by specializing systems through hardware accelerators purposefully built for machine learning and data analysis algorithms. However, data science evolves at a quick pace, and manual design of custom accelerators has high non-recurrent engineering costs: general solutions are needed to automatically and rapidly transition from the formulation of a new algorithm to the deployment of a dedicated hardware implementation. Our solution is the SOftware Defined Architectures (SODA) Synthesizer, an end-to-end, multi-level, modular, extensible compiler toolchain providing a direct path from machine learning tools to hardware. The SODA Synthesizer frontend is based on the multilevel intermediate representation (MLIR) framework; it ingests pre-trained machine learning models, identifies kernels suited for acceleration, performs high-level optimizations, and prepares them for hardware synthesis. In the backend, SODA leverages state-of-the-art high-level synthesis techniques to generate highly efficient accelerators, targeting both field programmable devices (FPGAs) and applicationspecific circuits (ASICs). In this paper, we describe how the SODA Synthesizer can also assemble the generated accelerators (based on the finite state machine with datapath model) in a custom system driven by a distributed controller, building a coarse-grained dataflow architecture that does not require a host processor to orchestrate parallel execution of multiple accelerators. We show the effectiveness of our approach by automatically generating ASIC accelerators for layers of popular deep neural networks (DNNs). Our high-level optimizations result in up to 74x speedup on isolated accelerators for individual DNN layers, and our dynamically scheduled architecture yields an additional 3x performance improvement when combining accelerators to handle streaming inputs.

show abstract

“…A number of experimental approaches in this direction [5,6,7] convert high-level operators from the Python-based frameworks into HLS code "templates" written in C/C++, which are then synthesized with commercial tools (Vivado HLS, Catapult C, etc), typically targeting field programmable gate arrays (FPGAs). The software defined accelerators (SODA) Synthesizer [8,9], instead, adopts a multi-layered, modular, fully open-source, compiler-based approach with a high-level frontend and optimizer based on the multi-level intermediate representation (MLIR) framework [10] to perform hardware/software decomposition and domain-specific transformation, and a synthesizer backend to generate custom Verilog modules that could target different device technologies (FPGAs from various vendors, as well as commercial and open-source application-specific integrated circuit -ASIC). In SODA, translation across different levels of abstraction is always performed with progressive lowerings between intermediate representations (IRs).…”

Section: Introductionmentioning

confidence: 99%

Automated Generation of Integrated Digital and Spiking Neuromorphic Machine Learning Accelerators

2021 IEEE/ACM International Conference on Computer Aided Design (ICCAD)

Song

et al. 2021

Self Cite