Automated Generation of Integrated Digital and Spiking Neuromorphic Machine Learning Accelerators

Abstract

The growing numbers of application areas for artificial intelligence (AI) methods have led to an explosion in availability of domain-specific accelerators, which struggle to support every new machine learning (ML) algorithm advancement, clearly highlighting the need for a tool to quickly and automatically transition from algorithm definition to hardware implementation and explore the design space along a variety of SWaP (size, weight and Power) metrics. The software defined architectures (SODA) synthesizer implements a modular compilerbased infrastructure for the end-to-end generation of machine learning accelerators, from high-level frameworks to hardware description language. Neuromorphic computing, mimicking how the brain operates, promises to perform artificial intelligence tasks at efficiencies ordersof-magnitude higher than the current conventional tensor-processing based accelerators, as demonstrated by a variety of specialized designs leveraging Spiking Neural Networks (SNNs). Nevertheless, the mapping of an artificial neural network (ANN) to solutions supporting SNNs is still a non-trivial and very device-specific task, and completely lacks the possibility to design hybrid systems that integrate conventional and spiking neural models. In this paper, we discuss the design of such an integrated generator, leveraging the SODA Synthesizer framework and its modular structure. In particular, we present a new MLIR dialect in the SODA frontend that allows expressing spiking neural network concepts (e.g., spiking sequences, transformation, and manipulation) and we discuss how to enable the mapping of spiking neurons to the related specialized hardware (which could be generated through middle-end and backend layers of the SODA Synthesizer). We then discuss the opportunities for further integration offered by the hardware compilation infrastructure, providing a path towards the generation of complex hybrid artificial intelligence systems.

Nonvolatile Memories in Spiking Neural Network Architectures: Current and Emerging Trends

“…While traditional von Neumann architectures have one or more central processing units physically separated from the main memory, neuromorphic architectures exploit the co-localization of memory and compute, near and in-memory computation [18]. Simultaneously to the tremendous progress in devising novel neuromorphic computing architectures, there has been many recent works that address how to map and compile (trained) SNNs models for efficient execution in neuromorphic hardware [19][20][21][22][23][24][25][26][27][28][29][30][31].…”

Implementing Spiking Neural Networks on Neuromorphic Architectures: A Review

“…In [139], Curzel et al propose an automated framework called SODASNN to synthesize a hybrid neuromorphic architecture consisting of digital and analog components. The framework consists of the software defined architecture (SODA) synthesizer [140], a novel no-human-in-the-loop hardware generator that automates the creation of machine learning (ML) accelerators from high-level ML language.…”

Design-Technology Co-Optimization for NVM-based Neuromorphic Processing Elements

“…PSOPART [27] minimizes spike latency on the shared interconnect, SpiNeMap [9] minimizes interconnect energy, DFSynthesizer [82] maximizes throughput, DecomposedSNN [11] maximizes crossbar utilization, EaNC [90] minimizes overall energy of a machine learning task by targeting both computation and communication energy, TaNC [89] minimizes the average temperature of each crossbar, eSpine [91] maximizes NVM endurance in a crossbar, RENEU [80] minimizes the circuit aging in a crossbar's peripheral circuits, and NCil [86] reduces read disturb issues in a crossbar, improving the inference lifetime. Beside these techniques, there are also other software frameworks [1,3,4,6,12,23,25,38,47,50,54,60,71,75,76,78,85,88] and run-time approaches [10,84], addressing one or more of these optimization objectives.…”