Towards an &amp;#x201C;early neural circuit simulator&amp;#x201D;: A FPGA implementation of processing in the rat whisker system

Leung, B.C.; Pan, Yan; Schroeder, Christopher L.; Memik, Seda Öǧrenci; Hartmann, Mitra J. Z.

doi:10.1109/fpl.2008.4629930

Cited by 2 publications

(1 citation statement)

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“…Hardware systems, which accelerate these spiking networks, including FPGA-based designs, are reviewed in [12] and [13]. These FPGA systems are predominantly time-stepped hardware accelerators as in [14]- [16], achieving high speeds but with performance proportional to the size of the network. Event-driven, sparser-computation hardware implementations, such as in [17]- [19] are rare, typically focusing on using biologically descriptive neuron models, such as the Izhikevich model [20] and biological network topologies.…”

Section: Introductionmentioning

confidence: 99%

Minitaur, an Event-Driven FPGA-Based Spiking Network Accelerator

Neil

Liu

2014

IEEE Trans. VLSI Syst.

211

129

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Current neural networks are accumulating accolades for their performance on a variety of real-world computational tasks including recognition, classification, regression, and prediction, yet there are few scalable architectures that have emerged to address the challenges posed by their computation. This paper introduces Minitaur, an event-driven neural network accelerator, which is designed for low power and high performance. As an field-programmable gate array-based system, it can be integrated into existing robotics or it can offload computationally expensive neural network tasks from the CPU. The version presented here implements a spiking deep network which achieves 19 million postsynaptic currents per second on 1.5 W of power and supports up to 65 K neurons per board.The system records 92% accuracy on the MNIST handwritten digit classification and 71% accuracy on the 20 newsgroups classification data set. Due to its event-driven nature, it allows for trading off between accuracy and latency.

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