Towards a software approach to mitigate voltage emergencies

Gupta, Manav; Rangan, K.K.; Smith, Michael D.; Wei, Gu-Yeon; Brooks, David

doi:10.1145/1283780.1283808

Cited by 47 publications

(28 citation statements)

References 10 publications

(17 reference statements)

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“…We have previously shown that there is a strong correlation between voltage violations and microarchitectural events [9]. A variety of events can lead to emergencies such as cache misses, pipeline flushes due to branch misprediction, TLB misses, and longlatency events.…”

Section: Introductionmentioning

confidence: 99%

An event-guided approach to reducing voltage noise in processors

Gupta¹,

Reddi²,

Holloway³

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Supply voltage fluctuations that result from inductive noise are increasingly troublesome in modern microprocessors. A voltage "emergency", i.e., a swing beyond tolerable operating margins, jeopardizes the safe and correct operation of the processor. Techniques aimed at reducing power consumption, e.g., by clock gating or by reducing nominal supply voltage, exacerbate this noise problem, requiring ever-wider operating margins. We propose an event-guided, adaptive method for avoiding voltage emergencies, which exploits the fact that most emergencies are correlated with unique microarchitectural events, such as cache misses or the pipeline flushes that follow branch mispredictions. Using checkpoint and rollback to handle unavoidable emergencies, our method adapts dynamically by learning to trigger avoidance mechanisms when emergency-prone events recur. After tightening supply voltage margins to increase clock frequency and accounting for all costs, the net result is a performance improvement of 8% across a suite of fifteen SPEC CPU2000 benchmarks. I. INTRODUCTIONPower-constrained CMOS designs are making it increasingly difficult for microprocessor designers to cope with power supply noise. As current draw increases and operating voltage decreases, inductive noise threatens the robustness and limits the clock frequency of high-performance processors. Large current swings over small time scales cause large voltage swings in the power-delivery subsystem due to parasitic inductance. A significant drop in supply voltage can cause timing margin violations by slowing logic circuits. For reliable and correct operation of the processor, voltage emergencies, i.e., large voltage swings that violate noise margins, must be avoided.The traditional way to deal with inductive noise is to over-design the processor to allow for worst-case fluctuations. Unfortunately, the gap between nominal and worstcase operating conditions in modern microprocessor designs is growing. A recent paper on supply-noise analysis for a POWER6 processor [11] shows the need for timing margins that accommodate voltage fluctuations of more than 18% of nominal voltage (200mV dips at a nominal voltage of 1.1V). Conservative design of processors using large timing margins ensures robustness, but it lowers the maximum achievable operating frequency.Another way to handle inductive noise is to design the processor for typical-case operating conditions and add a fail-safe mechanism that guarantees correctness despite noise margin violations. This strategy can improve performance, but only if the cost of using the fail-safe mechanism is not too high. In practice, active emergency prevention (e.g., performance throttling techniques) is needed if aggressive operating margins are sought to push performance.

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Section: Introductionmentioning

confidence: 99%

An event-guided approach to reducing voltage noise in processors

Gupta¹,

Reddi²,

Holloway³

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

View full text Add to dashboard Cite

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“…A number of papers dealt with mitigating voltage droops using software techniques [4][5] [16]. These techniques recognize the existence of repetitive code with high di/dt transition activity and dampen or eliminate this activity through software techniques.…”

Section: Previous Workmentioning

confidence: 99%

Performance boosting under reliability and power constraints

John¹,

Paul²,

Manne³

et al. 2013

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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We then examine the impact of FP throttling and guardband reduction on the SPEC CPU2006 benchmarks and show that some benchmarks benefit from the frequency improvements with FP throttling while others suffer due to reduced FP throughput.Finally, we present two techniques to determine dynamically when to trade FP throughput for reduced voltage margin and increased frequency, and show performance improvements of up to 15% for CINT2006 benchmarks and up to 8% for CFP2006 benchmarks. Our studies are done on hardware in which FP units generate the worst-case voltage droop. The technique can be modified for architectures in which other units cause the worst droop.

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“…However, most of these studies focused on prevention/avoidance [6][8], mitigation [12] [13], or recovery from the di/dt effect [10] [11]. In contrast, there are three previous works on creation of di/dt stressmarks to maximize voltage droop.…”

Section: Related Workmentioning

confidence: 99%

Automated di/dt stressmark generation for microprocessor power delivery networks

Kim

John

2011

IEEE/ACM International Symposium on Low Power Electronics and Design

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Abstract-In this paper, we propose a method for automated di/dt stressmark generation to test maximum voltage droop in a microprocessor power delivery network. The di/dt stressmark is an instruction sequence which draws periodic high and low current pulses that maximize voltage fluctuations including voltage droops. In order to automate di/dt stressmark generation, we devise a code generator with the ability to control instruction sequencing, register assignments, and dependencies. Our framework uses a Genetic Algorithm in scheduling and optimizing candidate instruction sequences to create a maximum voltage droop. The results show that our automatically generated di/dt stressmarks achieved more than 40% average increase in voltage droop compared to hand-coded di/dt stressmarks and typical benchmarks in experiments covering three microprocessor architectures and five power delivery network (PDN) models. Additionally, our method considers all the units in a microprocessor, as opposed to a previous ILP scheduling method that handles only execution units.Keywords -voltage droop; microprocessor power delivery network; di/dt stressmark; system-level power-aware design

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Towards a software approach to mitigate voltage emergencies

Cited by 47 publications

References 10 publications

An event-guided approach to reducing voltage noise in processors

An event-guided approach to reducing voltage noise in processors

Performance boosting under reliability and power constraints

Automated di/dt stressmark generation for microprocessor power delivery networks

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