Towards 5ps resolution TDC on a dynamically reconfigurable FPGA (abstract only)

Daigneault, Marc-Andre; David, Jean Pierre

doi:10.1145/1723112.1723161

Cited by 2 publications

(4 citation statements)

References 11 publications

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“…There are many TDC architectures [10][11][12], with various specifically targeting FPGA [8,9]. The simplest and commonly used approach is to use a counter registering the number of clock cycles since the beginning of the measurement.…”

Section: Time To Digital Convertermentioning

confidence: 99%

A low cost fluorescence lifetime measurement system based on SPAD detectors and FPGA processing

et al. 2017

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This work presents a low cost fluorescence life time measurement system, aimed at carrying out fast diagnostic tests through label detection in a portable system so it can be used in a medical consultation, within a short time span. The system uses Time Correlated Single Photon Counting (TCSPC), measuring the arrival time of individual photons and building a histogram of those times, showing the fluorescence decay of the label which is characteristic of each fluorescent substance. The system is implemented using a Xilinx FPGA which controls the experiment and includes a Time to Digital Converter (TDC) to perform measurements with a resolution in the order of tenths of picoseconds. Also included are a laser diode and the driving electronics to generate short pulses as well as a HV-CMOS implemented Single Photon Avalanche Diode (SPAD) as a high gain sensor. The system is entirely configurable so it can easily be adapted to the target label molecule and measurement needs. The histogram is constructed within the FPGA and can then be read as convenient. Various performance parameters are also shown, as well as experimental measurements of a quantum dot fluorescence decay as a proof of concept.

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Section: Time To Digital Convertermentioning

confidence: 99%

A low cost fluorescence lifetime measurement system based on SPAD detectors and FPGA processing

et al. 2017

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“…Programmable logic devices, especially FPGA and SoC, allow us to implement TDCs with different kinds of structures. Looking into the literature, we can roughly divide these architectures between TDCs based on feedback (FB) circuits, 34,35 e.g., ring-oscillators, and feedforward (FF) ones based on delay-lines. [34][35][36] The high difference of propagation delay values among combinatorial logic elements, mainly due to the scaling down of technology, favors the implementation of feedforward solutions with respect to the feedback ones.…”

Section: Tdc Ip-corementioning

confidence: 99%

“…Looking into the literature, we can roughly divide these architectures between TDCs based on feedback (FB) circuits, 34,35 e.g., ring-oscillators, and feedforward (FF) ones based on delay-lines. [34][35][36] The high difference of propagation delay values among combinatorial logic elements, mainly due to the scaling down of technology, favors the implementation of feedforward solutions with respect to the feedback ones. To confirm this, we can consider the worsening in resolution from 5 ps to 63.3 ps shown by two TDCs based on a ring-oscillator implemented in 28-nm 34 and 90-nm 35 technology, respectively.…”

Section: Tdc Ip-corementioning

confidence: 99%

“…[34][35][36] The high difference of propagation delay values among combinatorial logic elements, mainly due to the scaling down of technology, favors the implementation of feedforward solutions with respect to the feedback ones. To confirm this, we can consider the worsening in resolution from 5 ps to 63.3 ps shown by two TDCs based on a ring-oscillator implemented in 28-nm 34 and 90-nm 35 technology, respectively. Differently, a TDC based on delay-line offers a resolution of 75 ps in 130-nm, 36 50 ps in 90-nm, 37 and 39 The different propagation times of signals through the cascaded bins constituting a delay-line implemented in a FPGA device causes not uniform quantization.…”

Section: Tdc Ip-corementioning

confidence: 99%

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