Digital instrument with configurable hardware and firmware for multi-channel time measures

Lusardi, N.; Garzetti, F.; Geraci, A.

doi:10.1063/1.5028131

Cited by 29 publications

(23 citation statements)

References 44 publications

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“…The hardware complexity of propagating F replicas of a signal at this point made up of multiple edges on the same TDL suggests that a compromise between two extreme solutions of a single TDL and a TDL for each replica is the way that offers the best implementation efficiency. This is how a version of Wave Union A has been implemented in the IP-Core, in which f OU T TDLs are placed side by side in parallel each one performing E measures to give F = f OU T • E. This technique is known as Super Wave Union (SuperWU) [13], [35], [49]. Therefore, a reasonable compromise adopted in the IP-Core was the choice of SuperWU with two measures (E = 2) over four parallel TDLs, ( f OU T = 4), i.e.…”

Section: Figure 3 Schematic Of the Partition In Slices Of The Clbs In Last Generationmentioning

confidence: 99%

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Time-to-Digital Converter IP-Core for FPGA at State of the Art

et al. 2021

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The Field Programmable Gate Array (FPGA) structure poses several constraints that make the implementation of complex asynchronous circuits such as Time-Mode (TM) circuits almost unfeasible. In particular, in Programmable Logic (PL) devices, such as FPGAs, the operation of the logic is usually synchronous with the system clock. However, it can happen that a very high-performance specifications demands to abandon this paradigm and to follow an asynchronous implementative solution. The main driver forcing the use of programmable logic solutions instead of tailored Application Specific Integrated Circuits (ASIC), best suiting an asynchronous design, is the request coming from the research community and industrial R&D of fast-prototyping at low Non Recursive Engineering (NRE) costs. For instance in the case of a high-resolved Time-to-Digital Converter (TDC), a signal clocked at some hundreds of MHz implemented in FPGA allows implementing a TDC with resolution at ns. If a higher resolution is required, the signal frequency cannot be increased further and one of the aces up the designer's sleeve is the propagation delay of the logic in order to quantize the time intervals by means of a so-called Tapped Delay-Line (TDL). This implementation of TDL-based TDC in FPGAs requires special attention by the designer both in making the best use of all available resources and in foreseeing how signals propagate inside these devices. In this paper, we investigate the implementation of a high-performance TDL-TDC addressed to 28-nm 7-Series Xilinx FPGA, taking into account the comparison between different technological nodes from 65-nm to 20-nm. In this context, the term high-performance means extended dynamic-range (up to 10.3 s), high-resolution and single-shot precision (up to 366 fs and 12 ps r.m.s respectively), low differential and integral non-linearity (up to 250 fs and 2.5 ps respectively), and multi-channel capability (up to 16).

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Section: Figure 3 Schematic Of the Partition In Slices Of The Clbs In Last Generationmentioning

confidence: 99%

“…From an implementation point of view, the SuperWU is obtained instantiating f OU T TDLs ( [13], [35]) in parallel. The START signal is conveyed in a SuperWU-Launcher (SWUL) (Fig.…”

Section: Figure 3 Schematic Of the Partition In Slices Of The Clbs In Last Generationmentioning

confidence: 99%

Time-to-Digital Converter IP-Core for FPGA at State of the Art

et al. 2021

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“…CH1, CH2 and SYNC are each DC coupled with the input of a comparator (Analog Devices AD8465 [51]) whose threshold is regulated by a Digital-to-Analog Converter (DAC) (Analog Devices AD5694R [51]). The threshold voltage level can be set in the range 0-2.5 V in 4096 steps of 0.61 mV by means an I2C bus driven by the FPGA [18], [24]. This stage acts as a threshold discriminator converting the analog input pulses (0-3.3V) into Low Voltage Differential Signals (LVDS) with a timing jitter of less than 7 ps r.m.s.…”

Section: ) Analog Sectionmentioning

confidence: 99%

Digital Instrument for Time Measurements: Small, Portable, High–Performance, Fully Programmable

Corna¹,

Garzetti

Lusardi

et al. 2021

IEEE Access

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We present a small, portable, plug-and-play time measurement instrument entirely based on Field Programmable Gate Array (FPGA). Its performance is state-of-the-art in terms of the most recent Application-Specific Integrated Circuit (ASIC) solutions of Time-to-Digital Converters (TDCs), and all operating features are fully-programmable. The instrument offers an excellent cost-performance and is suitable for detector test and time correlation measurement applications. More generally, the instrument is very well suited for fast-prototyping of systems where time measures are involved, at low cost and design effort. All the features of the instrument can be easily accessed through either the Graphical User Interface (GUI) or directly from the software Application Programming Interface (API).

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“…Of the two methodologies, considering the consolidated trend towards multi-channel architectures, the digital one is certainly applied the most today as it offers the best performance in terms of noise immunity in an electromagnetic dirty environment such as a complex compact system [3], [4]. Moreover, the implementation of TDCs within configurable devices based on Programmable Logic (PL), such as Field Programmable Gate Arrays (FPGAs) [5] and System-on-Chips (SoCs) [6], has achieved the state-of-the-art in terms of performance, greatly improving system versatility [7]. This has led to a very intense research in recent years into TDC architectures designed for FPGA devices [8]- [10] and this is the reason why we refer in this discussion to this type of TDC as a case study.…”

Section: Introductionmentioning

confidence: 99%

“…Over a statistically significant number of measurements, any deviation from the uniform distribution of the measured values indicates non-linearity of the system. As is known, for TDCs non-linearity is quantified in the two parameters called Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) [7], [25].…”

Section: Introductionmentioning

confidence: 99%

Cross-Talk Issues in Time Measurements

Lusardi¹,

Corna

Garzetti

et al. 2021

IEEE Access

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The enormous diffusion of Time-Mode circuits, in particular Time-to-Digital Converter (TDC) time measurement circuits, and at the same time the dizzying increase in parallel channels required by the most recent applications, for example in the automotive and digital imaging fields, brings the problem of electromagnetic interference between channels ever more to the fore. This phenomenon, generally known as Cross-Talk (XT), is particularly critical given the increase in the operating frequency and density of systems components, and its effect on the timing parameters in TDC measurements is investigated. Considering the time measurements, XT creates temporal shift on the physical events from which the timestamps are extracted; in this manner, an error in the measurements is generated. In order to detect the XT phenomena, a methodical analysis based on Code-Density Test (CDT) is performed; in this terms, two different typologies of XTs are investigated, which are correlated and uncorrelated XT. Furthermore, a TDC board is used as case study and all the XT sources are detected and classified. Thus, a classification of the importance of the different sources of XT is achived and a solution to minimize the different causes is proposed.INDEX TERMS Cross-Talk (XT), Time Measurement, Time-to-Digital Converter (TDC), Code-Density Test (CDT), Linearity.

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Digital instrument with configurable hardware and firmware for multi-channel time measures

Abstract: A 6.6 ps RMS resolution time-to-digital converter using interleaved sampling method in a 28 nm FPGA Review of Scientific Instruments 90, 044706 (2019);

Cited by 29 publications

References 44 publications

Time-to-Digital Converter IP-Core for FPGA at State of the Art

Time-to-Digital Converter IP-Core for FPGA at State of the Art

Digital Instrument for Time Measurements: Small, Portable, High–Performance, Fully Programmable

Cross-Talk Issues in Time Measurements

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