Toward the Surface Preparation of InGaAs for the Future CMOS Integration

Lim, Sangwoo

doi:10.4028/www.scientific.net/ssp.282.39

Cited by 3 publications

(2 citation statements)

References 4 publications

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“…Due to their improved mobilities, SiGe, Ge, and III-V materials have mobilities of-40,000 cm 2 •V −1 s −1 for InGaAs (electron) and 1900 cm 2 •V −1 s −1 for Ge [1] (hole) compared to 1400 cm 2 •V −1 s −1 for electrons and 450 cm 2 •V −1 s −1 for hole of Si [272]. By entering the 10 nm technology node, the pure Si channel has been replaced with the abovementioned materials as listed.…”

Section: Wet Etch and Cleaningmentioning

confidence: 99%

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Radamson,

Miao,

Zhou

et al. 2024

Nanomaterials

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After more than five decades, Moore’s Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

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Section: Wet Etch and Cleaningmentioning

confidence: 99%

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Radamson,

Miao,

Zhou

et al. 2024

Nanomaterials

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show abstract

“…Beyond those inventions, the shape of CMOS has already been changed from planar to 3D by overcoming a lot of integration issues [ 4 ]. By entering the 10 nm technology node, pure silicon-based channel is being gradually replaced with silicon-germanium (SiGe) or germanium (Ge), and III-V materials, because they have better mobility of- 40,000 cm 2 V −1 s −1 for InGaAs (for electrons) and 1900 cm 2 V −1 s −1 for Ge (for holes) compared to 1400 cm 2 V −1 s −1 for electrons and 450 cm 2 V −1 s −1 for holes of silicon [ 5 , 6 ]. Not only are the channel materials changing, but so is device shape, from simple fin-like to fully depleted on insulator or nanowire ones [ 7 ].…”

Section: Introductionmentioning

confidence: 99%

State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

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Investigation of the Integration of Strained Ge Channel with Si-Based FinFETs

Wang

et al. 2022

Nanomaterials

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In this manuscript, the integration of a strained Ge channel with Si-based FinFETs was investigated. The main focus was the preparation of high-aspect-ratio (AR) fin structures, appropriate etching topography and the growth of germanium (Ge) as a channel material with a highly compressive strain. Two etching methods, the wet etching and in situ HCl dry etching methods, were studied to achieve a better etching topography. In addition, the selective epitaxial growth of Ge material was performed on a patterned substrate using reduced pressure chemical vapor deposition. The results show that a V-shaped structure formed at the bottom of the dummy Si-fins using the wet etching method, which is beneficial to the suppression of dislocations. In addition, compressive strain was introduced to the Ge channel after the Ge selective epitaxial growth, which benefits the pMOS transport characteristics. The pattern dependency of the Ge growth over the patterned wafer was measured, and the solutions for uniform epitaxy are discussed.

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Toward the Surface Preparation of InGaAs for the Future CMOS Integration

Cited by 3 publications

References 4 publications

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

State of the Art and Future Perspectives in Advanced CMOS Technology

Investigation of the Integration of Strained Ge Channel with Si-Based FinFETs

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