Toward High-Performance Digital Logic Technology with Carbon Nanotubes

Abstract

The slow-down in traditional silicon complementary metal-oxide-semiconductor (CMOS) scaling (Moore's law) has created an opportunity for a disruptive innovation to bring the semiconductor industry into a postsilicon era. Due to their ultrathin body and ballistic transport, carbon nanotubes (CNTs) have the intrinsic transport and scaling properties to usher in this new era. The remaining challenges are largely materials-related and include obtaining purity levels suitable for logic technology, placement of CNTs at very tight (∼5 nm) pitch to allow for density scaling and source/drain contact scaling. This review examines the potential performance advantages of a CNT-based computing technology, outlines the remaining challenges, and describes the recent progress on these fronts. Although overcoming these issues will be challenging and will require a large, sustained effort from both industry and academia, the recent progress in the field is a cause for optimism that these materials can have an impact on future technologies.

Kinetics modeling of nanoparticle growth on and evaporation off nanotubes

“…[1][2][3][4] Metallic CNTs can serve as interconnect electrodes for VLSI technology; 5 semiconducting CNTs may be utilized as the active channels of field effect transistors. 6,7 Understanding thermal properties of CNTs is essential for their applications in such platforms, and many studies have addressed this subject. 8 High electrical current in a suspended or on-substrate CNT introduces phonons and thermal effects, analysis of which is important in understanding transport properties.…”

“…Modeling NP growth on and sublimation off CNTs can offer guidance for developing protocols to successfully monitor the temperature profile in order to enable accurate extraction of thermal parameters of CNTs, and to design optimal interfaces for thermal management, enabling applications in novel low-power electronics designs. 7 Specifically, the design of the growth process can be optimized by kinetic Monte Carlo (MC) modeling predicting the time dependence of the particle sizes, particle-particle distance distribution statistics, and other properties dependent on the flux of matter and other controllable growth-process parameters, including the temperature. For the evaporation stage, process visualization and particle properties'-such as their linear dimensions-measurements can then be modeled.…”

Resist-free fabricated carbon nanotube field-effect transistors with high-quality atomic-layer-deposited platinum contacts

“…[3][4][5][6][7] Recent progress in growth, purification, and placement of carbon nanotubes demonstrates that the main hurdles for using carbon nanotubes in semiconductor applications are surpassable. [8][9][10][11][12] However, many challenges for reliable fabrication of CNTFETs still remain.…”

Variability and reliability analysis in self-assembled multichannel carbon nanotube field-effect transistors

“…Due to their small diameter and excellent transport properties, single-walled carbon nanotubes (CNTs) are a particularly attractive candidate. 4 While serious integration challenges remain, recent successes with gate-all-around geometries and sub-10 nm channel lengths are extremely encouraging. [5][6][7] Although the progress is impressive, the remaining technological barriers and process variation, including difficulty in assembling CNTs with a controlled pitch, imperfect semiconducting purity, on-state current (I on ) variation, threshold voltage (V t ) variation, 8 and contact resistance, 9 still limit the performance.…”