Consecutive multiline addressing (CMLA) has been developed to increase a PMOLED display's lifetime, resolution, and power efficiency. Mathematically, it decomposes an image matrix into a set of multiline matrices and a residual single-line matrix. The decomposition is lossless and implemented by a combinatorial algorithm allowing small chip size for the logic and high processing speed, e.g., for video applications. The additional memory needed for CMLA is just a fraction of the graphic data memory (GDRAM). The printed-circuit-board (PCB) prototype with a field programmable gate array (FPGA) proves that the CMLA produces images of the same visual quality as the conventional single-line addressing (SLA), while the power efficiency is substantially higher.