Total Ionizing Dose effects in 130-nm commercial CMOS technologies for HEP experiments

Gonella, L.; Faccio, F.; Silvestri, Marco; Gerardin, Simone; Pantano, D.; Re, V.; Manghisoni, M.; Ratti, L.; Ranieri, A.

doi:10.1016/j.nima.2007.07.068

Cited by 100 publications

(51 citation statements)

References 5 publications

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“…. Although the leakage current is not significant for the second process, there are likely to be significant differences between processes at the same technology node, as reported previously [4]. The differences are likely to be due to differences in the doping profile along the sidewall, the trapping quality of the STI oxide, the STI planarity, and/or the amount of stress.…”

Section: Comparison Of Off-state Leakage Current Variations For Diffementioning

confidence: 63%

“…This can be seen from the range of the data at a given dose, as well as the relative standard deviation (RSD). Variations in quantities such as doping concentration, transistor width, STI topology (planarity), and STI stress resulting from the contributions of process steps such as liner oxidation, high density-plasma oxide deposition, thermal oxidation processes after STI formation, and corner rounding effects in the STI [2][3][4][5][6][7][12][13][14][15] may contribute to the device-to-device variability as the dose increases.…”

Section: Comparison Of Off-state Leakage Current Variations For Diffementioning

confidence: 99%

“…This is particularly important in devices with relatively low threshold voltages. Post-irradiation off-state leakage current is usually a result of radiation-induced oxide trapped charge in the shallow trench isolation (STI), which can invert the p-substrate in nMOS transistors at the STI edges, thereby creating a leakage path between the drain and source [3][4][5][6]. In [1] it was shown that the standard deviation of the off-state leakage current increases with TID for devices with a particular threshold-voltage variant (low V t , or LVT) from a 90 nm technology, and in [7] the effect of channel width on TID-induced leakage current is investigated for the LVT devices from the same 90 nm technology.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

The impact of device width on the variability of post-irradiation leakage currents in 90 and 65 nm CMOS technologies

Rezzak

Maillard

Schrimpf

et al. 2012

Microelectronics Reliability

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Section: Comparison Of Off-state Leakage Current Variations For Diffementioning

confidence: 63%

Section: Comparison Of Off-state Leakage Current Variations For Diffementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

The impact of device width on the variability of post-irradiation leakage currents in 90 and 65 nm CMOS technologies

Rezzak

Maillard

Schrimpf

et al. 2012

Microelectronics Reliability

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“…Interestingly enough, the unirradiated sample degradation is the smallest one, showing a current drop of about 8% and a threshold voltage shift of about 25 mY. The sample irradiated at V gs = Vdd displays a larger radiation-induced degradation than the sample irradiated at V gs = gnd [2], [8], but a smaller one after the CRC stress. In particular, the first one displays a 20% drain current drop and a threshold voltage shift of 100 mV; the second exhibits a 25% drop and 180mV threshold voltage shift.…”

Section: Experimental and Devicesmentioning

confidence: 93%

Channel hot carrier stress on irradiated 130-nm NMOSFETs: Impact of bias conditions during X-ray exposure

Silvestri

Gerardin

Paccagnella

et al. 2007

2007 9th European Conference on Radiation and Its Effects on Components and Systems

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We investigate how X-ray exposure impact the long term reliability of 130-nm NMOSFETs as a function of device geometry and irradiation bias conditions. This work focuses on electrical stresses on n-channel MOSFETs previously irradiated with X-ray up to 136 Mrad(Si0 2 ) in different bias conditions. Irradiation is shown to negatively affect the degradation during subsequent hot carrier injection. Increasing the bias during irradiation slightly reduces the impact on electrical stress in core MOSFETs. We attribute these effects to an enhanced impact ionization at the bulk-STI interfaces due to radiation-induced trapped charge and defects.

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“…As an example, Fig. 2 shows the source-drain leakage current of minimum size NMOS transistors versus TID for samples in the 130 nm generation from three manufacturers [5]. The peaking of the leakage at doses of 1-3 Mrad has been studied in detail and attributed to the compensating contribution of negative charge trapped in defect states at the interface between the STI oxide and the silicon (that compensate for the holes trapped in the STI oxide) [6].…”

Section: E -04mentioning

confidence: 99%

Radiation Effects and Hardening by Design in CMOS Technologies

Faccio

2011

Analog Circuit Design

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Radiation threatens the correct functionality of electronics in space, avionics, nuclear and High Energy Physics (HEP) applications. The engineering community involved in each of these disciplines has developed over time its specific set of solutions to ensure system reliability. The specificity is dictated by requirements in terms of cost, accessibility and mission criticality of each component/system. In some cases, the selection and use of Commercial-Off-The-Shelf components (COTS) represents the cheapest and most practical solution. Nevertheless, the need for extensive irradiation campaigns in view of selecting first, then assuring reproducible radiation response of the components increases the cost and required testing resources. On the other hand, the development or purchase of dedicated "radiation-tolerant" components eases qualification and procurement and ensures the required level of reliability, but is typically more expensive. A small catalog of radiation-tolerant components is in fact accessible commercially at a cost/function ratio considerably larger than for COTS. This cost is in part determined by the need for using a dedicated manufacturing process (most often CMOS) qualified against radiation effects. The low volume of this market, together with its strict quality assurance requirements, make the business profitable for a small number of "niche" foundries only if silicon wafers can be sold at large prices for a relatively long time. Processes are therefore not phased out as quickly as in the commercial marketplace, and new developments take more time. As a result, they are typically lagging two generations or more behind commercial-grade products.An alternative approach, increasingly popular in the last decade, is based on the use of commercial standard CMOS technologies. Integrated Circuits (ICs) are designed with dedicated techniques to withstand radiation effects, an approach that is called "Hardness By Design" (HBD). This allows circuit designers to using state-of-the-art processes to design ICs, while at the same time delivering radiationtolerant components. In doing so, designers must be aware of the radiation effects H.

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Total Ionizing Dose effects in 130-nm commercial CMOS technologies for HEP experiments

Cited by 100 publications

References 5 publications

The impact of device width on the variability of post-irradiation leakage currents in 90 and 65 nm CMOS technologies

The impact of device width on the variability of post-irradiation leakage currents in 90 and 65 nm CMOS technologies

Channel hot carrier stress on irradiated 130-nm NMOSFETs: Impact of bias conditions during X-ray exposure

Radiation Effects and Hardening by Design in CMOS Technologies

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